Resistive Non-Volatile Memory Without Word-Line Overhead
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Solution Overview
Problem
Traditional embedded memories in semiconductor technology require additional word-lines and peripheral circuits, leading to increased power consumption, chip layout overhead, and cost inefficiencies due to complex manufacturing processes involving multiple lithographic masks.
Innovation Solution
A resistive non-volatile memory design utilizing a gate-resistively-changeable field effect transistor and a unipolar source/channel/drain diode implemented without a gate electrode, eliminating the need for word-lines and simplifying the chip configuration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional three-terminal active devices are used as control transistors, then memory functionality is achieved, but power consumption increases and chip layout overhead increases
Solution Approach 1:
The patent extracts and removes the gate electrode from the field-effect transistor structure, transforming it into a unipolar source/channel/drain diode. This elimination of the gate component directly reduces the number of required word-lines and peripheral circuits, thereby decreasing power consumption and chip layout overhead while maintaining memory functionality through the resistive change characteristics of the remaining structure.
Solution Approach 2:
The unipolar source/channel/drain diode structure performs multiple functions without requiring external gate control. The source/channel/drain region itself provides the resistive change mechanism that enables memory operation, eliminating the need for separate gate control circuits and reducing overall system complexity and power consumption.
2Reliability
If traditional three-terminal active devices are used as control transistors, then memory functionality is achieved, but chip layout overhead increases
Solution Approach 1:
By removing the gate electrode and transforming the three-terminal FET into a unipolar source/channel/drain diode, the patent eliminates the need for gate control wiring and associated peripheral circuits. This structural simplification directly reduces chip layout overhead and area requirements while preserving essential memory functionality.
3Ease of operation
If additional word-lines and peripheral circuits are added, then memory control is enabled, but device complexity increases
Solution Approach 1:
The patent removes the gate control mechanism entirely, replacing complex multi-line control structures with a simplified unipolar diode configuration. This extraction of the gate component directly reduces device complexity while maintaining memory control capabilities through alternative resistive change mechanisms.
4Reliability
If multiple lithographic masks are used for manufacturing, then embedded memory formation is achieved, but manufacturing cost increases
Solution Approach 1:
By eliminating the gate electrode structure, the patent simplifies the manufacturing process. The unipolar source/channel/drain diode can be formed with fewer lithographic masks and manufacturing steps compared to traditional FET-based memory structures, thereby reducing manufacturing cost while achieving embedded memory formation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design achieves ultra-scaled chip size, supports CMOS continual scaling, and enhances cost efficiency by reducing the complexity and power consumption of memory circuits.
Implementation Method 1
a gate-resistively-changeable field effect transistor... wherein a gate of the at least one gate-resistively-changeable field effect transistor is electrically connected to the at least one bit line
Data Source
AI summary
The present disclosure provides a resistive non-volatile memory, which includes at least one gate-resistively-changeable field effect transistor and a unipolar source/channel/drain diode. least The at one gate-resistively-changeable field effect transistor is electrically connected to at least one bit line. The unipolar source/channel/drain diode is implemented by a field effect transistor without the gate electrode. Two terminals of the unipolar source/channel/drain diode are electrically connected to a source line and the at least one gate-resistively-changeable field effect transistor.