Serial Read-Write Memory With Cleanup-Free Time Multiplexing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Modern processors with multiple cores sharing a single memory access port face speed limitations due to collisions, and multi-port memories increase die space and complexity with separate read and write ports.
Innovation Solution
A serial read write memory with time multiplexed cleanup and write operations, where bit lines in unselected columns are precharged during read operations, allowing simultaneous write operations without precharging selected columns, reducing power consumption and increasing speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If separate read and write ports are implemented in multi-port memories, then memory access speed is improved, but die space and device complexity increase
Solution Approach 1:
The memory is divided into multiple independent banks, each capable of autonomous read/write operations. This segmentation allows parallel access across banks while keeping individual bank structures simple, resolving the contradiction between speed and complexity by distributing the workload across multiple simplified units rather than complicating a single access port.
Solution Approach 2:
Read and write operations are merged into a single unified access port that handles both operations sequentially within the same physical structure. This eliminates the need for separate read/write ports and their associated transistors and wiring, reducing die space and complexity while maintaining full read/write functionality through time-multiplexed access.
2Productivity
If pseudo-dual-port memory uses double pumped word line operations, then read and write operations can occur in the same clock cycle, but power consumption increases due to repeated word line pulsing
Solution Approach 1:
Bit lines are precharged to a intermediate voltage level before the read operation begins. This preliminary action reduces the voltage swing required during subsequent read and write operations, allowing the word line to be pulsed once rather than twice, thereby reducing power consumption while maintaining the ability to perform both operations in the same clock cycle.
Solution Approach 2:
The bit line voltage levels are changed from traditional full-swing voltages to intermediate voltage levels during the precharge phase. This parameter change allows the memory to perform read and write operations with reduced voltage swings, decreasing the energy required for word line pulsing while maintaining operational throughput.
3Reliability
If cleanup operations are performed on selected columns before write operations, then data integrity is maintained, but operating speed decreases due to additional operation cycles
Solution Approach 1:
The bit lines are kept in a continuously precharged state throughout both read and write operations without requiring intermediate cleanup cycles. This continuous precharge state allows seamless transition between read and write operations on the same column, maintaining data integrity while eliminating the speed penalty of separate cleanup operations.
Solution Approach 2:
Bit lines are precharged to the appropriate state before read operations and maintained in that state for subsequent write operations. This preliminary and sustained precharging eliminates the need for separate cleanup operations, allowing write operations to proceed immediately after reads without sacrificing data integrity, thereby increasing operating speed.
Data Source
AI summary
A static random-access memory is provided with a double-pumped operation in which a read operation to a multiplexed group of columns of bitcells may occur in a first portion of a memory clock cycle and in which a write operation to a write-selected column in the multiplexed group of columns of bitcells may occur in a second portion of the memory clock cycle. The write operation to the write-selected column occurs without any precharging of bit lines in the write-selected column during read and write operations.