MRAM Two-Terminal Selectors for Compact SOT-MRAM Stacking
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Solution Overview
Problem
Existing MRAM technologies face challenges in optimizing the stacking efficiency and reducing the memory cell area to enhance memory density and operational efficiency, particularly in Spin-Orbit Torque MRAM (SOT-MRAM) devices.
Innovation Solution
The integration of a two-terminal read selector and a two-terminal write selector in a SOT-MRAM device, with specific layer configurations that reduce the number of stacked conductive layers and vertically stack the SOT conductor with the bit line, optimizing the device layout for improved stacking efficiency and reduced memory cell area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If conventional MRAM cell structure is used, then the basic memory function is achieved, but the memory cell area is large and stacking efficiency is low
Solution Approach 1:
The patent transitions from planar 2D layout to 3D vertical stacking by positioning the SOT conductor beneath the bit line and stacking conductive layers vertically. This dimensional change enables multiple memory cells to be stacked in the vertical direction, reducing the footprint area while maintaining or increasing total storage capacity. The vertical stacking of word lines, bit lines, and select lines in multiple layers achieves high-density integration without increasing cell area.
2Quantity of substance
If more conductive layers are stacked to improve memory density, then memory density increases, but the device complexity and manufacturing difficulty increase
Solution Approach 1:
The SOT conductor serves multiple functions: it generates spin-orbit torque for magnetic switching, acts as a conductive interconnect layer, and provides structural support for vertical stacking. The bit line and word line structures also serve dual purposes as both interconnects and magnetic field generation elements. This multi-functionality reduces the need for separate dedicated layers, thereby increasing memory density without proportionally increasing device complexity.
Solution Approach 2:
The patent merges the SOT conductor with the bit line structure by positioning the SOT conductor directly beneath the bit line, allowing these two functional elements to share vertical space. Similarly, multiple word lines and select lines are merged into vertical stacks where adjacent lines serve different functions (read select, write select, word line) but occupy overlapping vertical positions. This merging reduces the total number of discrete layers required compared to conventional separated structures.
3Ease of manufacture
If the SOT conductor is positioned above the bit line, then the basic device structure is simple, but the stacking efficiency is reduced and memory cell area increases
Solution Approach 1:
Instead of positioning the SOT conductor above the bit line as in conventional structures, the patent inverts this arrangement by placing the SOT conductor beneath the bit line. This inversion enables the bit line to be formed first in the lower layer, followed by vertical stacking of the SOT conductor and subsequent conductive layers above it. This inverted configuration optimizes the vertical stacking sequence for manufacturing while maximizing stacking efficiency and minimizing cell area.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances memory density and operational efficiency by minimizing the cell area and improving the conductive layer stacking, allowing for more SOT-MRAM devices to be deposited within a given thickness limitation.
Implementation Method 1
the flow of an electric current through the conductive layer generates a spin-orbit torque which is used to manipulate a magnetic state of the magnetic tunnel junction of the memory cell
Implementation Method 2
The resistance of the magnetic tunnel junction depends upon the relative alignment of the magnetization of the two ferromagnetic layers
Data Source
AI summary
A memory device includes a spin-orbit torque (“SOT”) conductor, a magnetic tunneling junction (“MTJ”) structure above the SOT conductor, a two-terminal read selector above the MTJ structure, a two-terminal write selector above the MTJ structure, and a bit line below the SOT conductor. The two-terminal read selector is conductively connected to the pinned layer in the MTJ structure. The two-terminal write selector is conductively connected to a first terminal of the SOT conductor. The bit line is conductively connected to a second terminal of the SOT conductor.