Semiconductor Memory DM Impedance Control via Mode Registers
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Solution Overview
Problem
The existing test modes for semiconductor memory devices, such as DDR5 SDRAM, do not adequately define the output driver state for the Data Mask Pin (DM), leading to circuit processing errors during impedance testing.
Innovation Solution
A control method that utilizes first and second Mode Registers (MRs) to directly define the impedance of the DM in a test mode, eliminating the need for an output driver state definition and related control circuits, allowing for accurate impedance testing without errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the existing test mode is used for DM pin, then the test mode can be implemented, but circuit processing errors occur during impedance testing
Solution Approach 1:
The patent changes the impedance parameter of the DM pin from its default termination state to an output driver state by controlling the impedance to be less than 100 ohms. This parameter change enables the DM pin to be compatible with the preset test mode without causing circuit processing errors, thereby improving both test reliability and mode compatibility.
2Measurement precision
If the output driver state is defined for DM pin, then impedance testing can be accurate, but device complexity increases
Solution Approach 1:
The patent makes the first and second MRs related to the DQ pin universally applicable to control the impedance of both the DQ pin and the DM pin. This multi-functionality allows the same MRs to define impedance parameters for different pins, eliminating the need for separate output driver state definitions and control circuits for the DM pin, thus achieving accurate impedance testing without increasing device complexity.
Solution Approach 2:
The patent merges the control function of the DM pin impedance into the existing MR control mechanism used for the DQ pin. By allowing the first and second MRs to directly define the impedance of the DM pin, the patent combines the control logic for both pins into a unified system, reducing overall control circuit complexity while maintaining measurement precision.
Data Source
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AI summary
Embodiments of the present disclosure provide a control method, a semiconductor memory, and an electronic device. When the semiconductor memory is in a preset test mode, a first Model Register (MR) and a second MR related to a Data Pin (DQ) are allowed to directly define the impedance of a Data Mask Pin (DM). The DM does not need to add definition of an output driver state and a related control circuit for the preset test mode to ensure that the preset test mode is adapted to the DM. The impedance of the DM may be tested in the preset test mode to avoid circuit processing errors.