Semiconductor Word-Line Testing with Bit-Line Mismatch Cancellation
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Solution Overview
Problem
The narrowing spacing between bit line pairs in semiconductor devices leads to variations in voltage levels, causing reliability issues in input and output data due to changes in adjacent bit line pairs, resulting in connection defects between word lines and bit lines.
Innovation Solution
A semiconductor device with a control circuit that deactivates the word line during a test mode, generates matching control signals and sense amplifier drive signals, and activates the word line after a settling period, using a sense amplifier to drive bit lines and inverted bit lines to the same voltage level and sense voltage differences to detect connection defects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the spacing between bit line pairs is narrowed to increase storage density, then the storage capacity is improved, but the voltage levels of bit line pairs vary due to changes in adjacent bit line pairs, causing connection defects
Solution Approach 1:
The patent applies preliminary action by performing a mismatch cancellation operation before the actual data read operation. The control circuit deactivates the word line, drives bit line pairs to the same voltage level (first voltage level), waits for a settling period, and then activates the word line for reading. This preliminary equalization of bit line voltages prevents voltage mismatches from causing connection defects during subsequent operations.
Solution Approach 2:
The patent changes the voltage parameter of the bit line pairs dynamically. During the mismatch cancellation operation, the control circuit drives bit line pairs to a specific first voltage level (different from the second voltage level used during normal operations). This parameter change equalizes the voltage levels across different bit line pairs, eliminating voltage variations that would otherwise cause connection defects.
2Productivity
If the word line is activated immediately after mismatch cancellation, then the operation speed is improved, but voltage differences between bit line pairs cause connection defects
Solution Approach 1:
The control circuit performs a preliminary settling period after driving bit line pairs to the same voltage level before activating the word line. This waiting period ensures that voltage differences between bit line pairs are fully eliminated, preventing connection defects while maintaining efficient operation timing.
Solution Approach 2:
The control circuit monitors the voltage levels of bit line pairs during the mismatch cancellation operation and adjusts the timing of word line activation accordingly. The feedback mechanism ensures that the word line is activated only after voltage equilibrium is achieved, preventing defects while optimizing speed.
Data Source
AI summary
A semiconductor device includes a control circuit configured to deactivate a word line during an active operation during a test mode, generate a matching control signal and a sense amplifier drive signal, and activate the word line after a settling period during the test mode, and a sense amplifier configured to drive a bit line and an inverted bit line to a same voltage level based on the matching control signal during the mismatching cancellation operation, and sense and amplify a voltage difference between the bit line and the inverted bit line based on the sense amplifier drive signal when the word line is activated after the settling period during the test mode.