Cross-Point Memory Arrays for Bipolar Access with Simplified Peripherals
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Solution Overview
Problem
Peripheral circuitry for bipolar memory devices is larger and more complex due to the need to support current and voltage in opposite polarities, leading to inefficiencies in accessing memory cells.
Innovation Solution
A memory apparatus and method for bipolar RRAM devices that utilize a cross-point memory array with chalcogenide materials, incorporating a selector element and a storage element, and employ specific biasing techniques to efficiently switch memory cells between resistance states using opposite polarities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If bipolar memory devices use peripheral circuitry to support current and voltage in opposite polarities, then the memory cells can be switched between resistance states, but the peripheral circuitry becomes larger and more complex
Solution Approach 1:
The patent inverts the conventional approach by using the memory array rows and columns themselves to generate the opposite polarity voltages needed for bipolar switching, rather than using external peripheral circuitry. Specifically, one line is driven to a first voltage level while the orthogonal line is driven to a second voltage level of opposite polarity, allowing the array structure to provide the bidirectional voltage support internally.
Solution Approach 2:
The patent makes the memory array lines serve multiple functions: they act as both data access lines and voltage generation lines for bipolar switching. The rows and columns are used universally for both selecting memory cells and providing the opposite polarity voltages required for setting and resetting the variable resistance materials, eliminating the need for dedicated peripheral circuitry.
2Adaptability or versatility
If bipolar memory devices use peripheral circuitry to support opposite polarities, then memory cells can be accessed in both directions, but the peripheral circuitry size increases
Solution Approach 1:
Instead of using external circuitry to generate opposite polarity voltages, the patent inverts the approach by using the memory array's own row and column lines to generate these voltages. The system drives one line to a first voltage level and the orthogonal line to a second voltage level of opposite polarity, allowing the array structure itself to provide bidirectional voltage support without additional peripheral components.
Solution Approach 2:
The patent merges the functions of data access lines and voltage generation lines into a single integrated system. The row and column lines that normally only carry data signals are combined with voltage generation capability, allowing them to simultaneously perform data access and provide the opposite polarity voltages needed for bipolar switching operations.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables efficient access operations in bipolar RRAM devices by simplifying the peripheral circuitry and reducing complexity, allowing for stable switching between resistance states with minimal circuit overhead.
Implementation Method 1
Electrical resistance of such variable resistance materials can change between a plurality of resistance states in response to electrical signals, such as, for example voltage or current pulses
Implementation Method 2
the resistance of a memory cell can change in one direction (e.g. from a high resistance to a low resistance) in response to a first electrical signal having a first polarity, and change in an opposite direction
Data Source
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AI summary
The disclosed technology generally relates to apparatuses and methods of operating the same, and more particularly to cross point memory arrays and methods of accessing memory cells in a cross point memory array. In one aspect, an apparatus comprises a memory array. The apparatus further comprises a memory controller configured to cause an access operation, where the access operation includes application of a first bias across a memory cell of the memory array for a selection phase of the access operation and application of a second bias, lower in magnitude than the first bias, across the memory cell for an access phase of the access operation. The memory controller is further configured to cause a direction of current flowing through the memory cell to be reversed between the selection phase and the access phase.