Memory Array Connections Using FEOL-to-BEOL Vertical Routing
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Solution Overview
Problem
Memory devices face challenges in efficiently connecting memory arrays to peripheral circuits due to limited metal routing channels and inefficient use of memory cells, leading to reduced area efficiency and higher costs.
Innovation Solution
The implementation of front-end-of-line (FEOL) peripheral circuits connected to back-end-of-line (BEOL) memory arrays through middle-end-of-line (MEOL) conductive layers, with conductive paths extending in the z-axis, allowing all memory cells to be utilized and reducing the area occupied by memory arrays and peripheral circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If memory arrays are connected to peripheral circuits using traditional metal routing channels, then the device structure is simple, but the area efficiency is reduced and memory cell utilization is inefficient
Solution Approach 1:
The patent transitions from planar (2D) metal routing connections to three-dimensional (3D) vertical conductive path connections. Memory arrays are positioned above peripheral circuits with conductive paths extending in the z-axis direction, enabling vertical interconnection through multiple metal layers and vias. This dimensional change allows efficient use of memory cells while reducing the footprint area occupied by both memory arrays and peripheral circuits.
2Productivity
If all memory cells are utilized with FEOL peripheral circuits connected to BEOL memory arrays, then area efficiency and memory cell density increase, but the device complexity increases due to additional conductive layers and vertical interconnections
Solution Approach 1:
The patent divides the device into distinct front-end-of-line (FEOL) and back-end-of-line (BEOL) sections, with peripheral circuits in the FEOL layer and memory arrays in the BEOL layer. The interconnection structure is segmented into multiple conductive layers (first, second, third metal layers) with vias connecting them sequentially. This segmentation allows independent optimization of each layer while managing complexity through modular construction.
Solution Approach 2:
The patent implements a nested structure where conductive paths are formed within conductive layers that are themselves within the broader device structure. Vias penetrate through dielectric layers to connect nested conductive layers, creating a doll-like nested arrangement where each conductive layer is embedded within the overall interconnection architecture, allowing efficient vertical routing while organizing complexity hierarchically.
Data Source
AI summary
A device includes a substrate, a first sense amplifier disposed on the substrate, a first word line driver disposed on the substrate and situated adjacent the first sense amplifier in the x-direction, and a first memory array disposed above the first sense amplifier and above the first word line driver in the z-direction. A plurality of first conductive segments extend alternately in the x-direction and the y-direction, and are disposed between the first memory array and the first sense amplifier and configured to electrically connect the first sense amplifier to a first bit line of the first memory array. A plurality of second conductive segments extend alternately in the x-direction and the y-direction, and are disposed between the first memory array and the first word line driver and configured to electrically connect the first word line driver to a first word line of the first memory array.