Bonded MRAM Arrays With Shared Driver Circuit Integration

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Solution Overview

Problem

Existing MRAM devices require multiple driver circuits for each memory array, increasing complexity and cost, and there is a need for a more efficient method to integrate multiple MRAM arrays while sharing a common driver circuit.

Innovation Solution

A bonded assembly of memory dies is formed, where each die includes a two-dimensional memory array of MRAM cells and access lines, with a common driver circuit driving both arrays through electrically conductive paths across a horizontal bonding interface, reducing the number of required driver circuits.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If multiple driver circuits are used for each memory array, then the memory arrays can operate independently and reliably, but the device complexity and cost increase

Engineering Contradiction:
Improvememory array operation reliabilityVSAvoiddriver circuit quantity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent merges multiple driver circuits into a single shared driver circuit that controls multiple MRAM arrays. The bonded assembly architecture allows one driver circuit to drive access lines for multiple memory arrays through the bonded interface, reducing the total number of driver circuits while maintaining operational reliability through shared control infrastructure.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The driver circuit is designed with universal functionality to control multiple different MRAM arrays. The single driver circuit can selectively address and control different memory arrays through the bonded assembly interface, enabling one circuit to perform multiple functions that would traditionally require separate dedicated circuits for each array.

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Adaptability or versatility

If multiple driver circuits are used for each memory array, then each array has dedicated control, but the manufacturing cost increases

Engineering Contradiction:
Improvededicated array control capabilityVSAvoidmanufacturing cost
Core Design Contradiction:
Adaptability or versatilityVSEase of manufacture

Solution Approach 1:

The patent combines multiple control functions into a single driver circuit unit, reducing the total component count and associated manufacturing costs. The bonded assembly structure enables cost-effective integration by allowing one driver circuit to serve multiple arrays, eliminating the need to manufacture and assemble separate driver circuits for each memory array.

Inventive Principle:
Principle #5Merging (Combining)

3Measurement precision

If multiple driver circuits are used, then control precision for each array is maintained, but the overall system complexity increases

Engineering Contradiction:
Improvearray control precisionVSAvoidsystem architecture complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The bonded assembly interface acts as an intermediary that enables a single driver circuit to precisely control multiple memory arrays. The bonding structure provides the necessary electrical connections and signal routing to maintain control precision while simplifying the overall system architecture by eliminating redundant driver circuit components.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS12581665B2Bonded memory MRAM arrays sharing a common driver circuit and methods of making the same
Publication Date: 2026.03.17 SANDISK TECHNOLOGIES LLC
  • US12581665B2 patent drawing
  • US12581665B2 patent drawing
  • US12581665B2 patent drawing

AI summary

A bonded assembly of a first memory die and a second memory die is provided. The first memory die includes a first two-dimensional memory array of first MRAM cells, first access lines, second access lines, a first driver circuit configured to drive the first access lines, and a second driver circuit configured to drive the second access lines and third access lines. The second memory die includes a second two-dimensional memory array of second MRAM cells, the third access lines, and fourth access lines. Each of the third access lines is electrically connected to a respective one of the second access lines via first electrically conductive paths that extend through a horizontal interface between the first memory die and the second memory die.