Bonded Processor-SRAM Stack for Lower RC Delay
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Solution Overview
Problem
The increasing size of microprocessors and the significant resistive-capacitive (RC) delay from the cache to the processor core degrade performance, with interconnect RC delay and SRAM yield being dominant factors.
Innovation Solution
A semiconductor device with a processor and SRAM cache integrated on a bonded chip, utilizing short-distance vertical metal interconnects instead of long-distance routing, reducing chip size and RC delay, and enhancing data transfer speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If cache is placed closer to processor core, then data transfer speed is improved, but chip area is increased
Solution Approach 1:
The patent transitions from planar (2D) cache organization to three-dimensional (3D) stacked architecture. Multiple cache layers are vertically stacked above the processor core, utilizing the vertical dimension to increase cache capacity and reduce access distance simultaneously. This dimensional change allows cache to be physically closer to the core while maintaining expanded capacity without proportionally increasing the chip's footprint area.
2Loss of time
If interconnect distance is reduced, then RC delay is decreased, but manufacturing precision is increased
Solution Approach 1:
The patent implements preliminary alignment mark formation on both the processor substrate and cache stack substrates before the bonding process. These alignment marks are created during fabrication, allowing for precise registration and alignment during the subsequent bonding step. This preliminary preparation enables accurate positioning of the stacked components, reducing the precision requirements during the actual bonding operation while achieving the necessary sub-micron alignment for short interconnect distances.
Solution Approach 2:
The patent introduces alignment marks as intermediary features that facilitate precise bonding between the processor core and cache stacks. These marks serve as reference points that mediate the alignment process, enabling accurate positioning without requiring direct measurement or complex real-time adjustment mechanisms during bonding.
3Reliability
If cache size is increased, then processor performance is improved, but chip complexity is increased
Solution Approach 1:
The patent divides the cache into multiple separate stacks, each containing a portion of the total cache capacity. These segmented cache stacks are individually fabricated and then bonded to the processor core in a systematic arrangement. This segmentation allows for modular design, independent optimization of each cache portion, and simplified fabrication processes compared to creating a single large monolithic cache structure.
Solution Approach 2:
The patent utilizes vertical stacking to organize cache memory, transitioning from horizontal expansion to vertical arrangement. Multiple cache layers are stacked above the processor core, with each layer accessible through vertical interconnects. This three-dimensional organization increases cache capacity and improves performance by reducing access distance, while the modular stacked architecture actually simplifies the overall chip design and fabrication compared to traditional planar expansion.
Data Source
AI summary
In an example, a semiconductor device includes a first semiconductor structure including a device layer, a first interconnect layer, and a first bonding layer. The device layer includes a processor and a logic circuit, and the first bonding layer includes a first bonding contact. The semiconductor device also includes a second semiconductor structure including an array of static random-access memory (SRAM) cells, a second interconnect layer, and a second bonding layer including a second bonding contact. The first bonding contact is in contact with the second bonding contact. The processor is electrically connected to the array of SRAM cells through the first interconnect layer, the first bonding contact, the second bonding contact, and the second interconnect layer. The logic circuit is electrically connected to the array of SRAM cells through the first interconnect layer, the first bonding contact, the second bonding contact, and the second interconnect layer.