Bonded Semiconductor Structure for Logic-RF Vertical Integration
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Solution Overview
Problem
The integration of logic devices and RF devices into a single substrate is challenging due to their different electrical properties and temperature tolerances, leading to difficulties in reducing the size of package structures and improving manufacturing processes.
Innovation Solution
A semiconductor structure is developed with two bonded substrates, one being an SOI substrate, where logic devices are formed over a bulk substrate and RF devices are vertically stacked, allowing for reduced product size and overcoming integration issues by using hybrid bonding and conductive vias for electrical connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If logic devices and RF devices are integrated into a single substrate, then product size is reduced, but manufacturing complexity increases due to different electrical properties and temperature tolerances
Solution Approach 1:
The patent divides the integrated circuit into two separate substrates: a first substrate for logic devices and a second substrate for RF devices. This segmentation allows each substrate to be optimized independently for its specific electrical properties and manufacturing requirements, while still achieving compact integration through wafer-level bonding.
Solution Approach 2:
The patent transitions from planar integration to three-dimensional vertical stacking by bonding the first substrate to the second substrate. This dimensional change enables both logic and RF devices to coexist in a compact footprint while maintaining their respective manufacturing optimizations.
2Volume of moving object
If different devices are integrated onto a single substrate, then product size is reduced, but integration reliability decreases due to electrical property conflicts
Solution Approach 1:
By separating logic devices and RF devices onto different substrates, the patent eliminates electrical property conflicts that would arise from integrating them on a single substrate. Each substrate can be designed with appropriate material properties, doping profiles, and process parameters optimized for its specific device type.
Solution Approach 2:
The patent introduces wafer-level bonding interfaces and interconnect structures as intermediaries between the logic and RF devices. These intermediaries provide controlled electrical connections while isolating the two device types from each other, maintaining reliability through controlled interfaces rather than direct integration.
3Ease of manufacture
If conventional integration methods are used, then manufacturing process is simpler, but product size reduction is limited
Solution Approach 1:
The patent employs wafer-level bonding to stack substrates vertically, transitioning from two-dimensional planar integration to three-dimensional integration. This enables significant product size reduction while maintaining compatibility with existing semiconductor manufacturing processes for fabricating individual substrates.
Solution Approach 2:
The patent performs preliminary fabrication of logic devices on the first substrate and RF devices on the second substrate using optimized processes for each device type. The substrates are then bonded together in a subsequent step, allowing each device type to be manufactured under ideal conditions before integration.
Data Source
AI summary
A semiconductor structure is provided. The semiconductor structure includes a first substrate and a second substrate. The first substrate includes a first semiconductor layer, including a first trench isolation that extends through a portion of the first substrate layer; and a first interconnect structure, disposed over the first semiconductor layer. The second substrate includes a second semiconductor layer, including a plurality of semiconductor islands and surrounded by at least a second isolation penetrating the second semiconductor layer; a second interconnect structure, disposed over the second substrate layer and bonded to the first interconnect structure; and a dielectric layer, disposed over the second semiconductor layer opposite to the second interconnect structure. A method of manufacturing the semiconductor structure is also provided.