Semiconductor Bonding Insulator Structure for Narrow-Pitch Chip Stacking
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Solution Overview
Problem
Insufficient bonding strength between chips and wafers in semiconductor devices, particularly in small chips with narrow pitch pads, leading to bonding failures and film elevation during heating processes, due to mixed pad and insulating regions on the bonding surface.
Innovation Solution
Incorporating a third insulating layer made of a material different from the first insulating layer to enhance bonding strength, using materials like SiN or SiCN for insulating layers in smaller chips to improve bonding strength and withstand voltage, and adjusting film thickness to manage thermal expansion differences.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If chip size is reduced to achieve downsizing, then miniaturization is achieved, but bonding strength becomes insufficient
Solution Approach 1:
The patent applies local quality by forming a bonding enhancement structure specifically at the bonding interface between chip and wafer. The protruding portion or recess structure is created only in the insulating layer at the bonding region, not throughout the entire chip. This localized structural modification enhances bonding strength precisely where needed without increasing overall chip size, thereby resolving the contradiction between miniaturization and bonding strength.
Solution Approach 2:
The patent implements preliminary action by pre-forming the bonding enhancement structure (protruding portion or recess) in the insulating layer before the bonding process. This advance preparation ensures that when bonding occurs, the enhanced interface structure is already in place to provide improved bonding strength, preventing bonding failures that would occur with simple direct bonding of reduced-size chips.
2Quantity of substance
If pad pitch is narrowed to increase terminal density, then terminal density is improved, but bonding reliability deteriorates
Solution Approach 1:
The patent applies local quality by creating bonding enhancement structures specifically at the bonding interface region, where the insulating layer forms protruding portions or recesses that improve bonding. This localized modification does not interfere with the narrow pad pitch configuration on the chip surface, allowing high terminal density to be maintained while bonding reliability is enhanced at the critical bonding interface.
Solution Approach 2:
The patent introduces an intermediary structural feature (the protruding portion or recess in the insulating layer) that acts as a mediator between the narrow pad structures and the bonding process. This intermediary structure provides mechanical interlocking and enhanced adhesion at the bonding interface, compensating for the reduced bonding area caused by narrow pad pitch while maintaining high terminal density.
3Strength
If insulating layer material is changed to enhance bonding strength, then bonding strength is improved, but manufacturing complexity increases
Solution Approach 1:
The patent applies parameter changes by modifying the physical structure (forming protruding portions or recesses) of the existing insulating layer rather than changing its material composition. This structural parameter modification enhances bonding strength through increased surface area and mechanical interlocking, while avoiding the complexity of material deposition, removal, or replacement processes that would be required if material composition were changed.
Data Source
AI summary
A semiconductor device according to one aspect of the present disclosure includes a semiconductor substrate having a first insulating layer and a plurality of first terminals provided on the first insulating layer, and a semiconductor element laminated on the semiconductor substrate and having a second insulating layer and a plurality of second terminals provided on the second insulating layer and connected to the plurality of first terminals, respectively. The first insulating layer or the second insulating layer includes a third insulating layer formed of a material different from a material of the first insulating layer and bonding the semiconductor substrate and the semiconductor element.