Bonding Layer Interconnect Layout for 3D Memory Routing Reduction
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Solution Overview
Problem
The increasing number of stacking layers in 3D memory devices leads to higher manufacturing costs and process complexity due to the demand for more back-end-of-line metal routing, which affects conductivity and increases resistance in metal traces.
Innovation Solution
The semiconductor structure incorporates a bonding layer with a combination of active and dummy bonding contacts, allowing some interconnection portions to be routed through the bonding layer, reducing the number of routing layers in the interconnection layer and maintaining trace width to minimize resistance and fabrication complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of stacking layers is increased to improve storage density, then storage density is improved, but manufacturing cost and process complexity increase due to more back-end-of-line metal routing
Solution Approach 1:
The patent routes interconnection portions through the bonding layer (vertical dimension) instead of only within the interconnection layer (horizontal dimension). This dimensional transition allows signal paths to bypass congested routing layers, reducing the number of required metal routing layers as stacking layers increase, thereby lowering process complexity while maintaining storage density improvements
2Reliability
If more back-end-of-line metal routing is added to support increased stacking layers, then electrical connectivity is maintained, but resistance increases and conductivity decreases due to reduced trace width
Solution Approach 1:
By transitioning routing from the horizontal interconnection layer to the vertical bonding layer, the patent creates shorter and more direct signal paths. This dimensional change reduces the total trace length and maintains adequate trace widths, thereby reducing resistance and improving conductivity while preserving electrical connectivity across increased stacking layers
3Reliability
If the number of routing layers is increased to accommodate more interconnections, then connectivity is improved, but fabrication complexity and manufacturing cost increase
Solution Approach 1:
The bonding layer is given a dual function: it serves both as a mechanical bonding interface between stacked structures and as an interconnection routing layer. This multi-functionality eliminates the need for additional dedicated routing layers, reducing fabrication complexity and manufacturing cost while maintaining comprehensive connectivity across all stacking layers
Data Source
AI summary
The present disclosure provides a semiconductor structure and a fabrication method thereof, a semiconductor device and a fabrication method thereof, and relate to the technical field of semiconductors. The semiconductor structure includes an interconnection layer and a bonding layer. The interconnection layer includes a first interconnection portion and a second interconnection portion. The bonding layer includes a bonding portion and a third interconnection portion. The first interconnection portion is connected with the second interconnection portion through the third interconnection portion. In the semiconductor structure provided by an example of the present disclosure, interconnection portions in the interconnection layer can be reduced by disposing the third interconnection portion in the bonding layer, thereby reducing the cost.