Semiconductor Bonding Pad Via Arrangement for Crack Prevention
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Solution Overview
Problem
The miniaturization of semiconductor integrated circuits leads to issues with pad electrode exfoliation from interlayer insulation films and damage to these films during wire bonding, due to stress applied during the bonding process, particularly with two-layer pad electrodes having metal vias in a matrix form.
Innovation Solution
A bonding pad configuration with multiple layers of pad electrodes electrically connected through vias, where vias are not arranged under the capillary end during wire bonding, preventing stress-induced cracks in the interlayer insulation film and maintaining adhesion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If vias are arranged in a matrix form all over the pad electrode to prevent exfoliation, then adhesion of pad electrode is improved, but cracks easily occur in the interlayer insulation film under the capillary end during wire bonding
Solution Approach 1:
The patent applies local quality by differentiating the via arrangement in different regions of the pad electrode. Vias are arranged in a matrix form in the peripheral region to prevent exfoliation, while the central region under the capillary end intentionally lacks vias to prevent crack formation during wire bonding. This localized differentiation resolves the contradiction between improving adhesion and preventing cracks.
Solution Approach 2:
The pad electrode area is segmented into two distinct regions: a peripheral region with via arrangement for adhesion enhancement, and a central region without vias to avoid stress concentration. This segmentation allows each region to fulfill its specific function without interfering with the other, solving the contradiction between adhesion improvement and crack prevention.
2Productivity
If pad electrode is miniaturized with high integration, then productivity is improved, but exfoliation of pad electrode from interlayer insulation film becomes remarkable
Solution Approach 1:
The patent applies local quality by concentrating via arrangements in the peripheral region of the miniaturized pad electrode, maximizing adhesion in the limited space available while maintaining the compact size required for high integration. This localized via placement prevents exfoliation without requiring increased overall pad size.
3Reliability
If stress is applied during wire bonding to form bonding ball, then bonding connection is achieved, but large stress damages the interlayer insulation film under the pad electrode
Solution Approach 1:
The patent applies local quality by creating a stress-free zone in the central region under the capillary end where the bonding process occurs. The absence of vias in this region prevents stress concentration and crack formation, allowing the necessary bonding stress to be applied without damaging the interlayer insulation film.
Solution Approach 2:
The patent implements beforehand cushioning by intentionally designing the central region without vias, which acts as a cushioning zone that absorbs and distributes the stress applied during wire bonding. This pre-designed stress distribution prevents crack formation in the interlayer insulation film before the bonding process occurs.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances the reliability of semiconductor devices by preventing cracks in the interlayer insulation film and maintaining adhesion, suitable for high-reliability semiconductor products like those used in vehicles.
Implementation Method 1
since an ultrasonic wave is applied to a bonding ball formed in a tip of bonding wire with a fixed load added by a capillary
Data Source
AI summary
To prevent cracks of an interlayer insulation film at the time of wire bonding while maintaining adhesion of an aluminum pad electrode and the interlayer insulation film in a semiconductor device in which the aluminum pad electrode and a lead frame are connected with bonding wire by a ball bonding technology. In a bonding pad that is configured to have multiple pad electrodes each with two or more layers, the pad electrodes being electrically connected with one another through vias, the vias are not arranged under an area to which a capillary end of a wire bonder contacts at the time of the wire bonding.