Relocating Bonding Structure to Substrate Bottom Surface
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Solution Overview
Problem
Low-K dielectric materials used in integrated circuit interconnect structures have poor mechanical strength, leading to cracking under bonding stresses and increased resistance with multiple metallization layers, which degrades device performance by causing higher RC delay and reducing speed.
Innovation Solution
The bonding structure is relocated from the top surface to the bottom surface of the substrate, with conductive interconnects formed through the substrate to connect metallization layers, reducing stress on fragile low-K dielectric interconnects and allowing for thinner interconnect structures, thereby enhancing mechanical stability and reducing resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If low-K dielectric materials are used in interconnect structures, then capacitance between interconnect lines is reduced, but mechanical strength deteriorates leading to cracking under bonding stresses
Solution Approach 1:
The interconnect structure is segmented into multiple functional layers: conductive interconnects for electrical connection, low-K dielectric layers for electrical isolation, and mechanical support structures (substrate and encapsulation layers) for structural integrity. This segmentation allows each layer to optimize its specific function without compromising overall system performance.
Solution Approach 2:
The patent employs a composite interconnect structure combining multiple materials with complementary properties: conductive materials (copper, aluminum, tungsten) for low resistance, low-K dielectric materials (silicon oxide, silicon nitride, fluorinated polymer) for low capacitance, and robust substrate materials for mechanical support. This composite approach resolves the contradiction by distributing functional requirements across different material layers.
2Adaptability or versatility
If the number of metallization layers is increased, then circuit complexity and functionality are improved, but connection wire lengths increase yielding higher resistance and RC delay
Solution Approach 1:
The patent transitions from planar interconnect routing to three-dimensional vertical stacking of metallization layers. This dimensional change allows signal paths to be shortened by routing connections vertically through the substrate rather than horizontally across the surface, thereby reducing RC delay while maintaining circuit functionality.
Solution Approach 2:
Different regions of the interconnect structure are optimized with locally appropriate properties: conductive interconnects with high electrical conductivity, low-K dielectric regions with optimized permittivity for signal isolation, and mechanical support regions with enhanced structural properties. This local optimization allows the system to achieve high functionality without proportionally increasing overall resistance.
3Reliability
If bonding structure is formed over the top surface interconnect structure, then wire bond connection is achieved, but stress is applied to fragile low-K dielectric inter level dielectrics causing cracking
Solution Approach 1:
Instead of forming the bonding structure over the top surface interconnects (conventional approach), the patent inverts the bonding architecture by forming conductive interconnects through the substrate and establishing bonding connections at the bottom surface. This inversion relocates the bonding stress away from the fragile low-K dielectric layers to the more robust substrate structure.
Solution Approach 2:
The substrate serves as an intermediary structure that decouples the bonding operation from the sensitive interconnect layers. By routing conductive paths through the substrate and establishing bonds at the opposite surface, the substrate mediates between the bonding process and the interconnect structure, protecting the low-K dielectric layers from direct mechanical stress.
Data Source
AI summary
An improved integrated circuit structure and method of making the same is provided. The integrated circuit structure comprises a substrate, the substrate having a top surface and a bottom surface. The top surface has a circuit device formed thereon. The structure includes a plurality of metallization layers, a bonding structure formed over the bottom surface and a conductive interconnect structure formed through said substrate.