Bootstrap Inverter Circuit for Full 0V and VDD Output
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Solution Overview
Problem
Conventional inverters configured only with N-channel transistors face issues where the output voltage is not completely zero when the inverter logic outputs '0', and the output voltage is lower than VDD when the inverter logic outputs '1'.
Innovation Solution
The proposed solution involves an inverter circuit that includes a first load transistor, a second load transistor, a driving transistor, and a control transistor, where the control transistor connects the source electrode of the first load transistor to ground when the gate electrode of the control transistor is turned on, ensuring the output voltage becomes 0V when necessary.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If an inverter is configured only with N-channel transistors to reduce device complexity and area, then the inverter structure is simplified and area is reduced, but the output voltage cannot reach complete 0V when logic outputs '0' and cannot reach VDD when logic outputs '1'
Solution Approach 1:
The load function is segmented into two separate transistors (first load transistor and second load transistor) instead of using a single transistor or resistor. This segmentation allows independent optimization of each transistor's role, enabling the output to reach complete logic levels while maintaining the N-channel only structure.
Solution Approach 2:
A control transistor is introduced as an intermediary element to actively manage the output voltage. The control transistor responds to the input signal and adjusts the circuit configuration to ensure the output reaches complete 0V or VDD levels, compensating for the limitations of the N-channel transistor structure.
2Area of stationary object
If a single load transistor is used to minimize area, then the inverter occupies less area, but the output voltage is determined by resistance ratios and cannot achieve complete logic levels
Solution Approach 1:
The load function is divided into two transistors connected in series between VDD and ground. This segmentation replaces the need for precise resistance ratio matching with a structure that naturally achieves complete logic levels through the series connection and control transistor action.
Solution Approach 2:
The control transistor automatically adjusts the circuit state based on the input signal. When the input is low, the control transistor turns off, allowing the output to be pulled to VDD through the load transistors. When the input is high, the control transistor turns on and pulls the output to complete 0V, eliminating the need for external voltage regulation.
3Device complexity
If the output voltage is determined by resistance ratios of transistors, then the circuit is simple, but the output current becomes small when the load resistance is large
Solution Approach 1:
The control transistor acts as an intermediary that provides a low-resistance path to ground when activated. This allows the output to reach complete 0V with high current capability, independent of the load transistor resistance values, thereby increasing output current capability without complicating the overall circuit structure.
Data Source
AI summary
The present invention relates to an inverter comprising: a first load transistor which has gate and drain electrodes connected to a power voltage (VDD) terminal; a second load transistor which has gate and drain electrodes connected to a source electrode of the first load transistor and has a source electrode connected to an output terminal; a driving transistor which has a drain electrode connected to the source electrode of the second load transistor to form the output terminal, has a gate electrode connected to an input (Vin) terminal, and has a source electrode connected to a ground (GND) terminal; and a control transistor which has a drain electrode connected to the source electrode of the first load transistor, has a gate electrode connected to the input (Vin) terminal, and has a source electrode connected to the ground (GND) terminal.