Bootstrapped Sample-and-Hold Circuit for Interleaved ADC Bandwidth Matching
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Solution Overview
Problem
High-speed interleaved ADCs face bandwidth mismatch and harmonic distortion issues due to mismatches in sampling capacitance and switch resistance, which are difficult to calibrate without degrading linearity or increasing circuit complexity.
Innovation Solution
A sample-and-hold circuit using a switched capacitor charge pump to tune the bootstrap capacitance voltage, allowing for bandwidth adjustment without degrading linearity or harmonic distortion, and requiring minimal additional circuitry.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If bandwidth mismatch calibration is performed by adjusting sampling capacitance or switch resistance, then bandwidth matching between channels is improved, but circuit complexity and parasitic capacitance increase
Solution Approach 1:
The patent changes the voltage parameter of the bootstrap capacitor rather than adjusting capacitance or resistance values. By controlling the bootstrap voltage level, the sampling circuit bandwidth is adjusted, achieving bandwidth matching between channels without adding complex circuitry or increasing parasitic capacitance. This parameter change approach resolves the contradiction by providing a simple voltage-controlled bandwidth adjustment mechanism.
2Reliability
If bootstrapped sampling switch is used to reduce harmonic distortion, then linearity is improved, but bandwidth matching becomes more difficult to maintain
Solution Approach 1:
The patent introduces dynamic control of the bootstrap voltage to simultaneously achieve both linearity and bandwidth matching. The bootstrap voltage is adjusted based on the specific channel's bandwidth requirements while maintaining the signal-independent switch resistance characteristic. This dynamic adjustment allows the bootstrapped switch to provide excellent linearity while the voltage tuning compensates for bandwidth mismatches between channels.
3Speed
If sampling switch resistance is reduced to improve bandwidth, then bandwidth is improved, but harmonic distortion increases
Solution Approach 1:
The patent changes the bootstrap voltage parameter to control the switch resistance dynamically. By optimizing the bootstrap voltage level, the switch achieves low on-resistance for high bandwidth while maintaining signal-independent resistance characteristic that reduces harmonic distortion. The voltage-controlled approach allows simultaneous optimization of both bandwidth and linearity without the trade-off present in fixed-resistance designs.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Achieves signal-independent bandwidth matching and improved harmonic linearity across a wide frequency range without increasing parasitic capacitance or requiring complex voltage DACs, thereby enhancing the performance of interleaved ADCs.
Implementation Method 1
a switched capacitor charge pump (22) to tune a voltage (Vch) of the bootstrap capacitance (21)
Data Source
Figure 1
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AI summary
The present invention relates to a sample-and-hold circuit (1) comprising - a transistor (11) arranged for switching between a sample mode and a hold mode, - a bootstrap circuit (2) arranged for maintaining in said sample mode a voltage level between a source terminal and a gate terminal of the transistor independent of the voltage at the source terminal and arranged for switching off the transistor in said hold mode, said bootstrap circuit comprising a bootstrap capacitance (21) arranged for being precharged to a given voltage during said hold mode, said bootstrap capacitance being connected between the source terminal and the gate terminal during said sample mode, characterised in that the bootstrap circuit comprises a switched capacitor charge pump (22) for generating that given voltage.