Electric Analogue Stores TRIZ Cases

By converting input voltage to current, this track-and-hold circuit avoids bootstrapping delays and improves ADC speed, linearity, and dynamic range.

Multi-level sensing uses a parallel ADC and access-history logic to correct voltage drift in NAND cells without read retries or added latency.

A current controlled oscillator and fast time-to-digital converter enable low-latency, linear voltage monitoring without fuse calibration.

Capacitive feedback in a differential memory sense path reduces charge sharing, cutting power use while preserving fast, reliable state detection.

A switched pre-charge circuit matches the sample node to the input voltage, cutting ADC acquisition time, disturbance, and average power.

Time-interleaved sub-ADCs are enabled or disabled by data rate to maintain recovery accuracy while avoiding unnecessary power use.

Operational-amplifier current sources stabilize memory-cell currents for accurate weighted-sum computing with less capacitor area and power.

Sequential charging and simultaneous discharging of differential nodes speed ADC conversion while keeping circuit complexity manageable.

An auxiliary buffer and replica capacitor mirror load current to keep input transistor current constant, improving linearity with lower power and area.

By sampling integrated copies of line current at two times, this circuit estimates inaccessible RC time constants and tunes drive voltage to cut delay.

Sampled bias currents are converted to stored voltage references to cancel sense amplifier offset and improve MRAM tail-bit read accuracy.

Pre-charged differential inputs cut hold time in low-voltage SerDes sampling, enabling higher data rates with lower power use.

A capacitive and switchable feedback path improves memory cell sensing by cutting charge leakage, power use, and read/write delay.

Selective sub-ADC activation matches receiver data rates, preserving phase linearity while reducing component usage and power.

Two capacitors split sampling and conversion across voltage domains, preventing parasitic diode charge loss and signal distortion.

Linear extrapolation using stored input and slew rate reduces track-and-hold dynamic error without DSP or delay-heavy filtering.

Floating-gate crossbar PUFs generate nonlinear, reconfigurable keys that resist machine learning attacks without stored secrets or error correction.

Decoupled common-mode voltages and switched-capacitor feedback help a track-and-hold amplifier maintain dynamic range despite transistor variation.

Offset-cancel feedback in a switched-capacitor DAC prevents bit errors when LSB voltage nears amplifier offset, improving flash failure-bit detection.

Bias-current sampling and stored voltage references cancel sense offset, helping MRAM read tail bits with tighter read margins.

Selective capacitive feedback switching limits charge sharing and power use while improving memory cell logic-state read accuracy.

A low-pass filter, track-and-hold, and averaging circuit demodulate PWM duty cycle with fast settling, low ripple, and no extra clock.

Lowering the NMOS gate high level and adding gate extensions with a shield line stabilizes on-resistance and cuts crosstalk.

AC coupling and autozeroing help DDR receivers cut VT drift while sustaining 18 Gbps bandwidth, low power, and tight timing margins.

A switched resistance and capacitor form an adjustable low-pass sample-and-hold stage that cuts aliasing under pulsed radar power.

Switched capacitors hold a divided voltage reference to isolate touch sensor channels from supply noise and improve measurement accuracy.

Native transistors counter leakage in a sample-and-hold circuit, extending voltage retention and reducing frequent sampling and power use.

An offset-biased, duty-cycled buffer reverse biases the sampling switch to cut leakage current, extend hold time, and lower power use.

A PMOS source follower and VSS-switched sampling stage cut leakage and feedthrough, improving linearity for high-speed wideband sampling.

Dual clock boost and differential cancellation cut parasitic distortion and leakage in top plate sample-and-hold ADC circuits.

Capacitive feedback and switched precharge isolate the memory cell during sensing, cutting charge sharing, leakage, and read power.

Switchable shared capacitors keep ADC voltage in range for accurate, low-power multi-channel touch sensing with reduced noise.

A compensation capacitor and differential transistor buffer cut AC input current, preserving ADC linearity at low voltage and power.

By splitting an analog optical input across photodetectors, this ADC raises sampling rate for RF signals without multiple parallel sampling heads.

Automatic signal-density metrics tune transceiver equalizers in real time to compensate channel corruption and improve link quality.

A switched capacitor charge pump tunes bootstrap voltage to match interleaved ADC bandwidth without harming linearity or adding circuit complexity.

Biasing the MOS switch substrate and electrode cuts hold-mode leakage while preserving fast capacitor charging in sample-and-hold circuits.