Differential ADC Architecture Balancing Simplicity and Speed
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Solution Overview
Problem
Analog-digital converters (ADCs) face a trade-off between configuration simplicity and operation speed, with successive approximation (SAR) ADCs being slow and flash ADCs being complex, necessitating the development of new types that balance these factors.
Innovation Solution
An analog-digital converter design that includes a first conversion unit for sequential charging and discharging of differential node pairs to generate upper digital data, and a second conversion unit performing phase interpolation operations to generate a thermometer code, which is then encoded to produce lower digital data, achieving a simple configuration and fast operation speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a successive approximation (SAR) ADC is used, then the configuration is simple, but the operation speed is slow
Solution Approach 1:
The ADC is divided into two functional units: a first ADC unit that sequentially charges differential node pairs to generate upper digital data, and a second ADC unit that simultaneously discharges differential node pairs to generate lower digital data. This segmentation allows different parts of the conversion process to operate in parallel, improving overall speed while maintaining relative configuration simplicity.
Solution Approach 2:
The ADC employs periodic sampling and alternating charge/discharge operations on differential node pairs. By periodically switching between sampling mode and conversion mode, and alternating between charging and discharging operations, the system achieves faster effective conversion rates while keeping the circuit architecture manageable.
2Speed
If a flash ADC is used, then the operation speed is fast, but the configuration is complicated
Solution Approach 1:
Instead of using a single complex flash ADC structure with numerous comparators, the invention segments the conversion process into two simpler ADC units with fewer comparators each. The first unit handles upper bit conversion while the second unit handles lower bit conversion, reducing overall configuration complexity while maintaining fast operation speed through parallel processing.
Solution Approach 2:
The ADC dynamically switches between different operational modes (sampling mode, first conversion mode, second conversion mode) and alternates between charging and discharging differential node pairs. This dynamic operation allows the system to achieve flash ADC-like speed with a simpler architecture by exploiting time-division multiplexing and differential signal processing.
3Device complexity
If sequential charging of differential node pairs is performed, then the configuration remains simple, but the conversion time increases
Solution Approach 1:
The system performs periodic sampling followed by alternating sequential charging and simultaneous discharging operations. By organizing operations in periodic cycles with distinct phases (sampling phase, first conversion phase, second conversion phase), the system minimizes total conversion time while keeping the sequential charging architecture simple.
Solution Approach 2:
While the first ADC unit is sequentially charging differential node pairs, the second ADC unit simultaneously performs discharging operations on other differential node pairs. This continuous parallel operation ensures that useful conversion work is being performed throughout the entire conversion cycle, reducing effective conversion time without complicating the individual unit designs.
Data Source
AI summary
An analog-digital converter includes a first analog-digital conversion unit configured to, during a first analog-digital conversion operation, sequentially charge each of n first differential node pairs, in response to a respective one of a differential sampling signal pair and first to (n−1)th differential signal pairs among n differential signal pairs, in response to each of the n first differential node pairs being sequentially charged, sequentially generate each of n first differential data pairs, and sequentially generate each of n upper differential data pairs to be used as n-bit upper digital data, in response to a respective one of the sequentially-generated n first differential data pairs. The first analog-digital conversion unit is further configured to, during a second analog-digital conversion operation, simultaneously discharge each of the n first differential node pairs, in response to a nth differential signal pair among the n differential signal pairs.