Current-Mode Track-and-Hold Circuit for High-Speed ADC Linearity
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Solution Overview
Problem
Sample-and-hold circuits limit linearity and dynamic range as signal speeds increase, particularly due to the need for bootstrapping and level-shifted clocks, which restrict conversion speeds in analog-to-digital converter systems.
Innovation Solution
A sample-and-hold circuit design that converts input voltage to current, eliminating the need for bootstrapping and level-shifted clocks, utilizing resistors, capacitors, inductors, and transistors to operate at high speeds while avoiding memory errors through feedforward compensation and discharge circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If bootstrapping technique is used to sample analog voltage with minimal distortion, then linearity is improved, but conversion speed is limited due to initial charging phase delay and tracking phase requirements
Solution Approach 1:
The patent extracts and eliminates the bootstrapping mechanism from the sample-and-hold circuit. By removing the bootstrap capacitor and associated control logic, the circuit avoids the initial charging phase delay and tracking phase requirements that limit conversion speed, while maintaining linearity through alternative circuit topology using current sources and resistors
Solution Approach 2:
The patent changes the operating parameters by using current-mode signal processing instead of voltage-mode bootstrapping. The input resistor converts input voltage to current, and current sources control the sampling and holding phases, eliminating the time-consuming voltage charging phases while preserving the linear relationship between input and output
2Manufacturing precision
If bootstrapping is implemented to ensure constant overdrive voltage independent of input voltage, then signal distortion is reduced, but additional transistors and capacitors are required increasing device complexity
Solution Approach 1:
The patent removes the bootstrap capacitor and the associated bootstrap control transistors from the circuit. The sampling switch is driven directly by a clock signal without requiring the bootstrap capacitor network, thereby reducing device complexity while maintaining signal integrity through current-mode operation
Solution Approach 2:
The patent substitutes the voltage-mode bootstrapping mechanism with a current-mode control system. Instead of using capacitors to maintain voltage levels, the circuit uses current sources to control the sampling switch, simplifying the device structure while achieving the same goal of minimizing signal distortion
3Productivity
If faster sampling and conversion speeds are achieved, then productivity is improved, but the time available for sampling and holding the input signal decreases limiting linearity
Solution Approach 1:
The patent enables continuous high-speed sampling by using current-mode operation that does not require the sequential charging and tracking phases of bootstrapping. The current sources can rapidly switch between sampling and holding states without the time delays associated with capacitor charging, maintaining linearity even at high conversion speeds
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables high-speed operation with improved linearity and dynamic range by eliminating the need for bootstrapping and level-shifted clocks, reducing memory errors, and maintaining fast conversion rates.
Implementation Method 1
A first current terminal of the first transistor is coupled to the first input resistor. The first current source device is coupled the first input resistor and to the first current terminal of the first transistor.
Data Source
AI summary
A sample-and-hold circuit includes a first input resistor, a first transistor, a first capacitor, a second resistor, and a first current source device. A first current terminal of the first transistor is coupled to the first input resistor. A first terminal of the first capacitor is coupled to the second current terminal of the first transistor at a first output node. A first terminal of the second resistor is coupled to the second terminal of the first transistor at the first output node. The first current source device is coupled the first input resistor and to the first current terminal of the first transistor.