Low-Voltage Input Buffer Circuit With Replica Current Linearity Compensation
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Solution Overview
Problem
Existing high-speed high-precision analog-to-digital converters face challenges in isolating package parasitic parameters and kick-back noises, requiring additional transistors to limit power supply voltage reduction and increasing power consumption, while also needing larger replica capacitors and extra load current mirror subcircuits.
Innovation Solution
A high-linearity low-voltage input buffer circuit with differential inputs, utilizing auxiliary buffers and a replica capacitor to generate and amplify a replica current, which compensates charge and discharge currents of the load capacitor, reducing the input load and power consumption without additional transistors or load current mirror subcircuits, and minimizing the replica capacitor size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a replica impedance is used to generate replica current to compensate load current, then linearity is improved, but additional transistors are needed which increases device complexity and limits power supply voltage reduction
Solution Approach 1:
The patent uses a replica capacitor Cc to create a copy of the load current effect. The replica capacitor generates a replica current that mirrors the load current, which is then amplified by the current mirror (transistors M3-M6) to compensate for the nonlinear effects on the input transistor. This copying approach maintains linearity without requiring additional transistors in the main buffer path.
Solution Approach 2:
The patent introduces an auxiliary buffer (transistors M1-M2) as an intermediary between the input signal and the main buffer. This auxiliary buffer isolates the input terminal from the direct impact of load current variations, allowing the replica current compensation mechanism to work effectively without adding complexity to the critical signal path.
2Manufacturing precision
If current mirror amplification is used to compensate load current, then linearity is improved and additional transistor in main buffer is avoided, but replica capacitor size increases and power consumption increases
Solution Approach 1:
The patent optimizes the replica capacitor size by changing the current mirror amplification factor. The current mirror (M3-M6) provides an amplification factor of N, allowing the replica capacitor Cc to be N times smaller than the load capacitor CL while still generating sufficient compensation current. This parameter adjustment reduces both the capacitor size and the power consumption of the compensation circuit.
3Manufacturing precision
If replica capacitor size is increased for current mirror amplification, then load current compensation is improved, but chip area increases
Solution Approach 1:
The patent reduces the replica capacitor size by utilizing the current mirror amplification effect. The current mirror (M3-M6) with amplification factor N allows the replica capacitor Cc to be designed with capacitance equal to CL/N, where CL is the load capacitor. This means the replica capacitor can be significantly smaller than the load capacitor while still providing adequate compensation, thereby reducing chip area.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively improves linearity by maintaining constant current through the input transistor, reduces the input load, and decreases power consumption and chip area by eliminating the need for extra transistors and load current mirror subcircuits, while minimizing the replica capacitor size.
Implementation Method 1
a replica capacitor Cc, wherein gates of the third transistor M3 and the fourth transistor M4 are respectively connected to the positive input terminal VIP and the negative input terminal VIN
Implementation Method 2
the third transistor M3 and the fourth transistor M4 form a current mirror with an amplification factor of N
Data Source
AI summary
Disclosed is a high-linearity low-voltage input buffer circuit. The buffer circuit includes main buffers of positive and negative input terminals comprised of NMOS transistor MN1 and MN3 as well as MN2 and MN6, auxiliary buffer comprised of PMOS transistors MP1 and MP3 as well as MP2 and MP4, replica current amplifier comprised of NMOS transistors MN3 and MN4 as well as MN5 and MN6. Two ends of a replica capacitor Cc are respectively connected with positive and negative output terminals of the auxiliary buffer. The auxiliary buffer is used to simulate a load effect of the main buffers to generate a replica current of a load current, then the replica current is mirrored to a load transistor of the main buffer by the current amplifier, and the load capacitor is charged and discharged through the load transistor.