Multi-Level Memory Cell Sensing for Voltage Drift Correction

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Solution Overview

Problem

Multi-level NAND memory systems face challenges with voltage drift over time, leading to high bit error rates due to reliance on static demarcation voltages, which can result in significant latency and performance degradation during data retrieval.

Innovation Solution

Implementing multi-level sensing technology with a 4-level parallel ADC in the read path, combined with a finite state machine for error correction, allows for accurate determination of memory cell values without retries, thereby eliminating latency and ensuring correct data retention.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If static demarcation voltages are used for multi-level NAND memory sensing, then device complexity is reduced, but measurement precision deteriorates due to voltage drift over time

Engineering Contradiction:

Improvesensing circuit complexityVSAvoidvoltage level detection accuracy

Core Design Contradiction:

Device complexityVSMeasurement precision

Solution Approach 1:

The patent implements dynamic sensing by using multiple demarcation voltages (first, second, and third demarcation voltages) that are applied sequentially at different times rather than a single static voltage. This allows the sensing circuit to adapt to voltage drift over time by comparing the memory cell voltage against multiple reference levels, thereby maintaining measurement precision without excessive complexity increase.

Inventive Principle:

Principle #15Dynamics

Solution Approach 2:

The patent changes the sensing parameters by using multiple demarcation voltages with different threshold levels instead of a single fixed voltage. The first demarcation voltage is used initially, and subsequent demarcation voltages are applied based on detected voltage drift, allowing the system to maintain accurate measurement by adjusting the reference parameters dynamically.

Inventive Principle:

Principle #35Parameter changes

2Measurement precision

If multi-level sensing with multiple demarcation voltages is implemented, then measurement precision is improved, but device complexity increases

Engineering Contradiction:

Improvevoltage level detection accuracyVSAvoidsensing circuit complexity

Core Design Contradiction:

Measurement precisionVSDevice complexity

Solution Approach 1:

The patent segments the voltage sensing process into multiple discrete steps, each using a specific demarcation voltage. Instead of using a single complex high-precision voltage comparator, the system divides the sensing into multiple simpler comparison operations against different reference voltages, making the overall system more manageable and implementable.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

Inventive Principle:

Principle #15Dynamics

3Reliability

If voltage demarcation retries are performed to correct bit errors, then reliability is improved, but loss of time increases due to latency

Engineering Contradiction:

Improvedata retrieval accuracyVSAvoiddata retrieval latency

Core Design Contradiction:

ReliabilityVSLoss of time

Solution Approach 1:

The patent performs preliminary sensing actions by initially detecting the voltage level using the first demarcation voltage and determining a preliminary value. This preliminary detection allows the system to identify potential errors early and apply corrections using subsequent demarcation voltages before final data retrieval, reducing the need for retries and associated latency.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The patent implements feedback by monitoring the detected voltage level against multiple demarcation voltages and adjusting the interpretation of the memory cell value based on the detected drift. The system uses the detected voltage level to determine whether to apply correction logic, creating a feedback loop that improves reliability while minimizing unnecessary retries and time loss.

Inventive Principle:

Principle #23Feedback

4Device complexity

If single-bit sensing is used in multi-level memory, then device complexity is reduced, but loss of information occurs due to voltage drift

Engineering Contradiction:

Improvesensing circuit complexityVSAvoiddata accuracy

Core Design Contradiction:

Device complexityVSLoss of information

Solution Approach 1:

Inventive Principle:

Principle #35Parameter changes

Data Source

PatentUS11264094B2Memory cell including multi-level sensing

Publication Date: 2022.03.01 INTEL CORP

AI summary

An embodiment of a semiconductor apparatus may include technology to convert an analog voltage level of a memory cell of a multi-level memory to a multi-bit digital value, and determine a single-bit value of the memory cell based on the multi-bit digital value. Some embodiments may also include technology to track a temporal history of accesses to the memory cell for a duration in excess of ten seconds, and determine the single-bit value of the memory cell based on the multi-bit digital value and the temporal history. Other embodiments are disclosed and claimed.