Sample-and-Hold Circuit Using Native Transistors for Longer Hold Time
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Solution Overview
Problem
Conventional sample-and-hold (S/H) circuits face limitations in hold time due to leakage currents, which restrict the duration they can maintain sampled analog signals, leading to increased power consumption and frequent sampling requirements.
Innovation Solution
The implementation of a S/H circuit using a single capacitor and strategically controlled switches, including native transistors, to minimize leakage currents and extend hold time, allowing for longer retention of sampled voltages and reduced power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Duration of action of stationary object
If conventional S/H circuits are used, then the circuit can sample analog signals, but the hold time is limited due to leakage currents
Solution Approach 1:
The patent converts the harmful leakage current into a beneficial effect by using a native transistor whose threshold voltage naturally compensates for the leakage. The native transistor's body effect creates a threshold voltage that increases as the hold capacitor voltage decreases, automatically counteracting the leakage current and extending hold time without additional power consumption.
Solution Approach 2:
The patent changes the electrical parameters of the holding circuit by using a native transistor with dynamically varying threshold voltage. As the capacitor voltage changes during the hold period, the native transistor's threshold voltage adjusts accordingly, optimizing the holding performance throughout the entire hold period and significantly extending the usable hold time.
2Duration of action of stationary object
If hold time is extended using conventional methods, then sampled values can be retained longer, but power consumption increases
Solution Approach 1:
The native transistor provides self-regulating leakage compensation without requiring external control signals or additional power. The transistor automatically adjusts its conduction based on the capacitor voltage through its inherent body effect, creating a self-sustaining holding mechanism that extends hold time while consuming minimal power.
3Duration of action of stationary object
If leakage current is reduced to extend hold time, then sampling frequency can be reduced, but circuit complexity increases
Solution Approach 1:
The patent merges the native transistor with the existing switch transistor, using the same transistor structure for both switching and holding functions. This integration approach extends hold time without adding separate dedicated holding components, thereby minimizing the increase in circuit complexity while achieving significant hold time improvement.
Data Source
AI summary
An apparatus includes a sample-and-hold (S/H) circuit. The S/H circuit includes a first switch to provide an input signal that is to be sampled, and a second switch coupled to receive the sampled signal. The second switch is further coupled to a capacitor. The S/H circuit further includes at least one native transistor coupled to the second switch and to the capacitor.