Sample-and-Hold Circuit Biasing for Longer Hold Time
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Solution Overview
Problem
Sample-and-hold (S/H) circuits in modern ICs face limitations in hold time due to leakage currents, which affect the accuracy and duration of holding sampled analog signals, and existing solutions do not effectively address the issue of power consumption during low-power modes.
Innovation Solution
The introduction of a S/H circuit with a buffer that intentionally adds an offset voltage and a duty-cycled buffer to reduce leakage current and power consumption, respectively, by using a skewed buffer to reverse bias the sampling switch and implementing a duty-cycled operation to minimize continuous power usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Duration of action of stationary object
If a conventional S/H circuit is used, then the circuit can sample and hold analog signals, but the hold time is limited due to leakage currents
Solution Approach 1:
The buffer is designed with an intentional offset voltage that creates a reverse bias condition on the sampling switch during the hold phase. This preliminary anti-action (reverse bias) counteracts the forward leakage current that would otherwise cause the held voltage to decay, thereby extending the hold time without requiring additional active compensation circuits.
Solution Approach 2:
The buffer's offset voltage is specifically designed and adjusted to change the biasing condition of the sampling switch from forward-biased (during sampling) to reverse-biased (during holding). This parameter change in the switch's operating state reduces the leakage current exponentially, as reverse-biased switches exhibit much lower leakage characteristics.
2Measurement precision
If the buffer operates continuously to maintain signal integrity, then signal accuracy is preserved, but power consumption increases
Solution Approach 1:
The buffer operates in a duty-cycled manner, being activated only during the sampling phase when signal accuracy is critical, and entering a low-power state during the hold phase. This periodic operation maintains signal integrity when needed while dramatically reducing average power consumption during the typically longer hold periods.
Solution Approach 2:
The buffer's operating state is dynamically changed between active and low-power modes based on the operational phase (sampling vs. holding). This dynamic adaptation allows the circuit to optimize between signal accuracy and power consumption in real-time, rather than operating in a fixed state.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed solution extends the hold time of sampled signals, reducing the need for frequent sampling and lowering power consumption, allowing for longer periods of low-power operation and improved circuit performance.
Implementation Method 1
a voltage source coupled to an input of the buffer to apply an offset voltage to the input of the buffer
Implementation Method 2
a first switch coupled to receive an input signal. The first switch is further coupled to a first capacitor
Implementation Method 3
a buffer coupled to the first switch
Data Source
AI summary
An apparatus includes a sample-and-hold (S/H) circuit. The S/H circuit includes a first switch coupled to receive an input signal. The first switch is further coupled to a first capacitor. The S/H circuit further includes a buffer coupled to the first switch. In addition, the S/H circuit includes a voltage source coupled to an input of the buffer to apply an offset voltage to the input of the buffer.