Top Plate Sampling Circuit With Dual Clock Boost for Low Distortion
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Solution Overview
Problem
Analog-to-digital converters in wireless communication devices face signal distortion and noise due to parasitic capacitance and harmonic distortions in sample-and-hold circuits, particularly when using top plate sampling techniques, which can lead to a low signal-to-noise ratio and implementation issues.
Innovation Solution
A sample-and-hold circuit employing a top plate sampling technique with input-dependent dual clock boost circuits and differential/common mode cancellation techniques to minimize distortions, using dual clock systems to prevent signal leakage and maintain constant switch resistance, and employing hold stage capacitive coupling to mitigate parasitic effects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If top plate sampling technique is used in sample-and-hold circuits, then sampling speed and circuit simplicity are improved, but signal distortion and noise increase due to parasitic capacitance and harmonic distortions
Solution Approach 1:
The patent converts the harmful parasitic capacitance effects into beneficial signal cancellation by using differential signaling. The parasitic capacitance affects both differential signals equally, creating common-mode noise that can be rejected through differential processing, thereby transforming the harmful parasitic effect into a manageable common-mode signal.
Solution Approach 2:
The patent introduces differential signaling as an intermediary mechanism between the sampling switch and the hold capacitor. By using differential pairs of signals and components, the system mediates the harmful parasitic effects through differential processing, where the parasitic capacitance becomes a common-mode disturbance that can be rejected rather than directly affecting the signal integrity.
2Device complexity
If conventional sample-and-hold circuits are used, then circuit complexity is reduced, but signal-to-noise ratio deteriorates due to parasitic capacitance effects
Solution Approach 1:
The patent segments the single-ended sampling circuit into differential pairs. Instead of using a single sampling switch and capacitor, the system uses paired differential switches and capacitors, where each pair handles one differential signal. This segmentation allows the parasitic capacitance effects to be distributed and canceled through differential processing, improving signal-to-noise ratio without significantly increasing overall circuit complexity.
3Device complexity
If single clock system is used in boost circuits, then circuit complexity is reduced, but signal leakage occurs causing distortion
Solution Approach 1:
The patent employs periodic dual-clock signaling to control the boost circuits, where one clock phase charges the boost capacitor and the other phase isolates it. This periodic action with two complementary clock phases ensures that the boost circuit provides the necessary voltage boost during sampling while preventing signal leakage during the hold phase, thereby eliminating distortion without requiring complex additional circuitry.
Data Source
AI summary
In some examples, a system includes a first transistor comprising a first source terminal coupled to a first input terminal, a first drain terminal coupled to a first top plate sampling capacitor, and a first gate terminal. The system also includes a first input-dependent dual clock boost circuit coupled to the first input terminal via a first boost circuit input and to the first gate terminal via a first boost circuit output. The system further includes a second transistor comprising a second source terminal coupled to a second input terminal, a second drain terminal coupled to a second top plate sampling capacitor, and a second gate terminal. The system also includes a second input-dependent dual clock boost circuit coupled to the second input terminal via a second boost circuit input and to the second gate terminal of the second transistor via a second boost circuit output.