Inner Sense Amplifier Sampling for MRAM Offset Cancellation
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Solution Overview
Problem
Conventional current sense amplifiers struggle to accurately read data from magnetic RAM (MRAM) due to narrow read margins at the tail bits of low-resistive and high-resistive state distributions, necessitating a solution for offset cancellation to enhance read yield requirements.
Innovation Solution
The implementation of an apparatus with first and second bias circuits and an inner amplifier, which includes current generators, transistor devices, and capacitors to replicate and store currents and voltages, allowing for sense amplifier offset cancellation by determining whether a bit memory element indicates a high or low resistive state during sampling and amplification phases.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional current sense amplifiers are used to read data from MRAM, then the reading operation can be performed, but the read margin is insufficient at the tail bits of LRS and HRS distributions resulting in inaccurate data reading
Solution Approach 1:
The patent applies preliminary action by performing offset cancellation before the actual read operation. The sense amplifier circuit executes a calibration phase where it measures and stores offset values from dummy MTJs, then subtracts these offsets from the actual read measurements. This preliminary compensation enables accurate detection of tail bits that would otherwise be indistinguishable, directly resolving the contradiction between measurement precision and read yield reliability
Solution Approach 2:
The patent introduces intermediary elements (dummy MTJs and reference circuits) that serve as mediators to characterize and compensate for circuit offsets. These dummy MTJs are identical to actual storage MTJs but are used solely for calibration purposes, providing a reference measurement that mediates the correction of systematic errors in the sense amplifier, thereby improving both precision and reliability without affecting actual data storage
2Measurement precision
If offset cancellation is implemented to improve read accuracy at tail bits, then measurement precision increases, but device complexity increases due to additional circuits
Solution Approach 1:
The patent merges the offset cancellation functionality with the existing sense amplifier circuit by integrating dummy MTJs and reference circuits into the same physical structure. The calibration and read operations share common circuit elements such as current sources and switching networks, allowing offset compensation to be achieved without adding completely separate circuit blocks. This merging approach improves tail bit detection accuracy while minimizing the increase in overall device complexity
Data Source
AI summary
In a particular implementation, an apparatus including first and second bias circuits and an inner amplifier provides sense amplifier offset cancellation. The inner amplifier includes: first and second current generators configured to replicate respective first and second currents from the first and second bias circuits, first and second transistors configured to transform the first and second currents into voltage samples, and first and second capacitors configured to store the voltage samples. In a sampling phase, a sampling of the first and second currents may be performed in the inner amplifier, and further, in an amplification phase, an amplification of the stored voltage samples may also be performed in the inner amplifier.