Sample-Hold CMOS Switch Layout for Stable On-Resistance
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Solution Overview
Problem
CMOS switches in sample hold circuits exhibit significant power supply voltage dependency in on-resistance, leading to fluctuations in charging speed and operation speed, due to parasitic capacitances and charge injection effects.
Innovation Solution
The solution involves adjusting the gate signal high level of the NMOS transistor to a voltage lower than the power supply voltage and using a gate voltage adjustment circuit to maintain this lower voltage, while extending the gates of the NMOS and PMOS transistors wider than their channel width and incorporating a shield line to reduce parasitic capacitances and crosstalk.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the gate signal high level of the NMOS transistor is set to the power supply voltage, then the on-resistance is low and charging speed is fast, but the on-resistance exhibits significant power supply voltage dependency causing fluctuations in operation speed
Solution Approach 1:
The patent changes the gate signal high level parameter from the power supply voltage to a lower fixed voltage level. This parameter change reduces the power supply voltage dependency of the on-resistance while maintaining sufficiently low resistance values for fast charging, thereby stabilizing operation speed without sacrificing charging performance
2Object-affected harmful factors
If the gate width of the NMOS and PMOS transistors is increased to reduce parasitic capacitances, then the charge injection effect is reduced, but the device area increases
Solution Approach 1:
The patent extends the gate width locally beyond the channel width specifically at the regions where parasitic capacitances are generated. This localized extension targets the problematic areas (gate-drain and gate-source overlap regions) without requiring a uniform increase in the entire transistor area, thus reducing parasitic capacitances while minimizing area overhead
3Object-generated harmful factors
If a shield line is added to reduce crosstalk and parasitic capacitances, then noise and crosstalk are minimized, but the device complexity and area increase
Solution Approach 1:
The patent introduces a shield line as an intermediary element between the NMOS and PMOS transistors. This shield line acts as a mediator that blocks electromagnetic coupling and reduces crosstalk between the transistors. The shield line is implemented as a simple conductive structure connected to a fixed potential, adding minimal complexity while effectively suppressing noise and interference
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the power supply voltage dependency of the on-resistance, stabilizes the on-resistance, and minimizes noise and crosstalk, resulting in improved operation speed and reduced noise characteristics of the sample hold circuit.
Implementation Method 1
A high level of a gate signal of the NMOS transistor is adjusted to a voltage level lower than a power supply voltage of a chip on which the CMOS switch is integrated
Implementation Method 2
extending the gates of the NMOS and PMOS transistors wider than their channel width and incorporating a shield line to reduce parasitic capacitances and crosstalk
Implementation Method 3
incorporating a shield line to reduce parasitic capacitances and crosstalk
Data Source
AI summary
A sample hold circuit includes at least one capacitor CS and at least one complementary metal-oxide semiconductor (CMOS) switch. The CMOS switch includes an N-channel metal-oxide semiconductor (NMOS) transistor and a P-channel metal-oxide semiconductor (PMOS) transistor connected in parallel. A high level of a gate signal VGN of the NMOS transistor is adjusted to a voltage level VREG lower than a power supply voltage VDD of a chip on which the CMOS switch is integrated.