Zero-Hold-Time Sampler for Low-Voltage SerDes Receivers
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Solution Overview
Problem
Existing sampling circuits in serializer/deserializer (SerDes) receivers face limitations in low-voltage applications, where the hold time increases with decreasing supply voltage, limiting frequency operation and increasing power consumption.
Innovation Solution
A sampling circuit incorporating a latching circuit with pass-gate transistors and capacitive elements, which pre-charge differential inputs, allowing for reduced hold time and enhanced frequency operation independent of supply voltage levels, utilizing a combination of NMOS and PMOS transistors to manage clock signals and voltage levels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If conventional sampling circuits are used in low-voltage applications, then power consumption is reduced, but hold time increases which limits frequency operation
Solution Approach 1:
The sampling circuit pre-charges the differential input nodes to a predetermined voltage level before the sampling operation. This preliminary action ensures that the nodes are ready to capture the differential signal quickly, reducing the hold time required to maintain valid sampled data even at low supply voltages where power consumption is minimized
2Device complexity
If conventional sampling circuits are used, then circuit simplicity is maintained, but frequency operation is limited due to increased hold time at low voltages
Solution Approach 1:
The sampling circuit dynamically adjusts the voltage levels at the differential input nodes by pre-charging them to an optimized voltage level. This parameter change enables the circuit to operate at higher frequencies by reducing the time required to maintain valid sampled data, while the circuit topology remains relatively simple
3Use of energy by moving object
If low supply voltage is used to reduce power consumption, then power efficiency improves, but hold time increases limiting data rate
Solution Approach 1:
The circuit performs preliminary pre-charging of the differential input nodes to establish optimal voltage levels before sampling. This preliminary action compensates for the effects of low supply voltage, enabling the circuit to maintain short hold times and achieve high data rates while operating efficiently at low voltages for improved power efficiency
4Speed
If hold time is reduced for high-frequency operation, then frequency capability increases, but voltage levels must be increased increasing power consumption
Solution Approach 1:
The sampling circuit changes the voltage parameter by pre-charging the differential input nodes to an optimized voltage level that is independent of the supply voltage. This parameter change enables the circuit to achieve short hold times for high-frequency operation without requiring increased supply voltage, thereby maintaining low power consumption
Data Source
AI summary
Certain aspects of the present disclosure generally relate to a sampling circuit, such as a sampling circuit for a low-voltage differential signaling (LVDS) serializer/deserializer (SerDes) system. One example sampling circuit generally includes a latching circuit and a plurality of pass-gate transistors. The latching circuit includes differential inputs, differential outputs, a clocked input circuit coupled to the differential inputs, a first cross-coupled circuit coupled to the clocked input circuit, and a second cross-coupled circuit coupled to the first cross-coupled circuit, wherein the first and second cross-coupled circuits are coupled to the differential outputs of the latching circuit. Each pass-gate transistor is coupled between one of the differential inputs of the latching circuit and a corresponding differential input of the sampling circuit.