Track-and-Hold Circuit Linearization for Leakage-Free Hold Mode
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Solution Overview
Problem
High-speed track-and-hold amplifiers suffer from signal distortion and low linearity due to current leakage and hold-mode feedthrough, with current technologies unable to completely turn off the source follower and prevent parasitic capacitance effects, resulting in limited spurious-free dynamic range performance.
Innovation Solution
A high-speed track-and-hold device incorporating a PMOS source follower and post-linearization technique, with a PMOS source follower acting as a buffer to block tail current feedback and a cross-coupled circuit to eliminate parasitic capacitance, and a sampling stage with a switch connected to VSS to minimize leakage current, ensuring complete shutdown during hold mode.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a switched source follower structure is used to achieve high-speed sampling, then sampling speed is improved, but current leakage occurs causing signal distortion and degraded signal quality
Solution Approach 1:
The patent extracts and removes the tail current source that causes incomplete turning off of the source follower. By eliminating this harmful current source, the source follower can be completely turned off during hold mode, preventing current leakage and hold-mode feedthrough while maintaining high-speed sampling capability
Solution Approach 2:
The patent applies preliminary anti-action by using a pre-amplifier stage that actively compensates for and prevents current leakage before it affects the sampling capacitor. The pre-amplifier is designed to ensure complete turning off of the source follower, preemptively preventing the harmful effects of leakage current on signal integrity
2Object-generated harmful factors
If a CS amplifier is used as a buffer to prevent previous stage from being affected, then stage isolation is improved, but transconductance (Gm) effects cause 3rd order harmonic distortion reducing SFDR performance
Solution Approach 1:
The patent replaces the complex CS amplifier buffer with a simpler source follower buffer that achieves sufficient isolation without introducing significant transconductance effects. This simpler buffer structure maintains stage isolation while avoiding the 3rd order harmonic distortion that degrades SFDR performance
Solution Approach 2:
The patent changes the buffer configuration from CS amplifier to source follower, altering the electrical characteristics to reduce transconductance effects. Additionally, the patent optimizes transistor sizing and biasing parameters to minimize Gm-related distortion while maintaining buffer functionality
3Speed
If the source follower is not completely turned off in hold mode, then switching speed is maintained, but hold-mode feedthrough transmits input signal changes to sampling capacitor
Solution Approach 1:
The patent extracts and removes the tail current source that prevents complete turning off of the source follower. This elimination enables the source follower to be fully turned off during hold mode, blocking feedthrough paths while maintaining fast switching capability through optimized switch design
Data Source
AI summary
Disclosed is a high-speed track-and-hold device including a buffer stage circuit including a PMOS source follower and a post linear circuit, and a sampling stage circuit that is responsible for supplying a source voltage (VSS) to the buffer stage circuit and that is arranged so that a switch connected to a gate is connected to the source voltage (VSS) and the NMOS transistor of a sampling stage is turned off in hold operation.