Top-Plate Bootstrapped Sample-and-Hold for Wideband ADC Linearity
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Solution Overview
Problem
Conventional sample and hold circuits in analog-to-digital converters face challenges in achieving high-speed, high-resolution, and wide frequency range linearity, especially in 5G and millimeter wave applications, with limitations in bandwidth, power efficiency, and signal-to-noise ratio.
Innovation Solution
The implementation of a top-plate bootstrapped sampling circuit with a voltage doubler circuit and specific transistor configurations, including PMOS and NMOS transistors, to provide a clock signal that enables distortion-free sampling and holding of analog signals, achieving 11-12 bit linearity over a wide frequency range and robust performance across process, voltage, and temperature corners.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional sample and hold circuits are used in ADCs, then basic sampling function is achieved, but bandwidth and signal-to-noise ratio are limited
Solution Approach 1:
The sample and hold circuit is segmented into two independent plates: a top plate for sampling and a bottom plate for holding. This segmentation allows the sampling operation to be performed on the top plate while the bottom plate maintains the held value, enabling higher bandwidth operations without degrading the signal-to-noise ratio during the holding phase.
Solution Approach 2:
A bootstrapped clock signal serves as an intermediary mechanism that simultaneously controls the sampling and holding operations. The clock signal is bootstrapped from the top plate itself, creating an intermediate voltage reference that enables precise timing control and isolates the sampling transient effects from the holding capacitor, thereby maintaining high signal-to-noise ratio while achieving wide bandwidth.
2Speed
If high-speed sampling is implemented, then bandwidth increases, but power consumption increases
Solution Approach 1:
The circuit employs periodic clock signals to control the sampling and holding operations. By using periodic action rather than continuous operation, the circuit achieves high-speed sampling only when needed (during the sampling phase) while remaining in a low-power holding state during the conversion phase, thereby reducing overall power consumption while maintaining high sampling speed capability.
Solution Approach 2:
The top plate is bootstrapped to generate part of its own clock signal, reducing the need for external high-power clock drivers. The sampling capacitor itself contributes to generating the clock signal that controls the switching, thereby reducing the power required for high-speed operation while maintaining the necessary sampling speed.
3Speed
If top-plate bootstrapped sampling is implemented, then bandwidth and linearity are improved, but circuit complexity increases
Solution Approach 1:
The top plate serves multiple functions: it acts as the sampling capacitor, the holding capacitor reference, and the source of the bootstrapped clock signal. This multi-functionality reduces the need for separate dedicated components for each function, thereby achieving wide bandwidth and high linearity while limiting the increase in circuit complexity through functional integration.
Solution Approach 2:
The sampling and clock generation functions are merged into a single bootstrapped mechanism. The clock signal is generated by bootstrapping from the top plate itself rather than requiring a separate clock generation circuit, which simplifies the overall circuit while achieving the desired bandwidth and linearity performance.
4Measurement precision
If distortion-free sampling is achieved through bootstrapping, then linearity improves to 11-12 bits, but device area increases
Solution Approach 1:
The bootstrapping mechanism maintains the top plate at a constant potential reference during the sampling phase, creating an equipotential condition that eliminates distortion. By keeping the sampling capacitor charged to a fixed reference voltage during sampling, the circuit achieves 11-12 bit linearity without requiring large compensation capacitors or additional correction circuits that would increase device area.
Data Source
AI summary
Described herein are systems and methods related to a device including an analog-to-digital converter (DAC) configured to convert a digital signal into an analog signal. The systems and methods can receive an analog signal at a first input, and provide the analog signal to a first output in response to a first clock signal. The first clock signal has a level at least partially dependent on the analog signal. The systems and methods can provide a path to a ground node for the first clock signal in response to a second clock signal. The second clock signal is independent of the analog signal.