Analogue/Digital Conversion TRIZ Cases

Filtered SD-ADC output is checked against a threshold to flag instability oscillations and support more reliable converter operation.

Filtered frequency-band monitoring and threshold comparison flag unstable SD-ADC output before oscillations corrupt trusted conversion results.

Chopped reference generation and low-pass filtering cut ADC noise in large thermopile arrays, improving thermal resolution with lower power.

Burst-signal preamble interpolation estimates clock phase offset, improving sampling alignment, SNR, and data recovery in optical receivers.

An NMOS-only double-cascode driver uses bleed paths and output networks to preserve gain and bandwidth while protecting photonic modulators from overvoltage.

Capacitor-coupled storage cells transfer controlled charge to bit lines, cutting voltage variation, power dissipation, and multiply error.

DAC-driven gate control tracks USB-C analog audio signals to keep MOSFET impedance stable and cut distortion during overvoltage isolation.

Modular RF sampling and DSP channels let MRI systems process multiple nuclear species beyond hydrogen for richer MR images and spectra.

Charge-sharing capacitors correct comparator mismatch offset quickly while keeping power low and reducing recalibration needs.

Parallel PGAs and a summing circuit create piecewise logarithmic compression that avoids clipping and keeps silicon microphone SNR nearly constant.

Rotating X and W data across analog MAC unit elements balances gain, cutting cumulative error and power in ML inference hardware.

Replica transimpedance and I/O circuits cancel leakage-current errors from switches and ESD paths, preserving conversion gain across voltage and temperature changes.

Adaptive filtering with upsampled interference signals compensates nonlinear and convolved sensor disturbances to improve output accuracy.

A dual-capacitor switching scheme suppresses voltage ripple and avoids op-amp oscillation to keep reference current generation stable.

A cascaded sinusoidal band-stop FIR approach removes time-varying signal components to deliver precise amplitude extraction with low latency.

Separating even and odd bit adjustment equalizes DWA component selection probability, reducing signal errors from process mismatch.

Branch predictor metadata and signature feedback tune on-chip mitigation to diffuse power and EM leakage with low latency and power cost.

Random offset codes keep delay stages away from mid-code INL peaks, cutting fractional spurs and deterministic jitter in retimers.

A two-stage switched feedback path stores amplifier offset on a capacitor to cut input current, reduce noise, and keep the circuit stable.

A voltage comparator replaces LED-based level detection to improve digital signal level conversion accuracy across a wider input range.

Edge detection with pulse skip and reset cleans quadrature encoder bounce without a fixed timer, preserving resolution across varying speeds.

A CDTA current-feedback buffer boosts ADC bandwidth while reducing parasitic-capacitance sensitivity, power draw, and timing limits.

A single isolation channel uses modified OOK and frequency-based demodulation to carry gate and configuration data with less power and silicon area.

A voltage-controlled delay circuit turns input voltage into clock timing, cutting comparator decision time and easing ADC hold timing.

Weight-controlled PAM4 output driving balances eye heights and level separation to improve high-speed signal reliability with low power.

Variable bit-cell activation in a DAC turns mismatch distortion into filterable pseudorandom noise, reducing popping and clicking.

Replacing analog multipliers with PLL-based digital mixing cuts circuit area, power use, and noise in physical quantity detection.

Dynamic reference voltage feedback helps a PAM-n receiver distinguish bit levels more accurately while supporting higher-speed, higher-capacity data links.

A DTC-based RF cancellation path generates anti-phase signals to suppress IMD3 and self-interference during concurrent high-power transmission.

A nonlinear DAC pre-compensates amplifier gain response, preserving precise gain steps while reducing DAC size, cost, and control complexity.

Precharging the sampling capacitor to a reference potential cuts amplifier-dependent settling time and lets sampling start sooner.

Edge-based sampling decodes a noisy touch-panel modulation signal faster, cutting stylus writing-trace display delay.

A voltage follower buffers the ramp reference across pixel circuits, reducing node variation and improving AD precision, dynamic range, and frame rate.

On-chip heating and PTAT-based analog compensation calibrate intercept and slope drift faster and cheaper than oven-based methods.

Coherent averaging turns RF ADC continuous wave spurs into removable periodic signals, cutting hardware complexity and LO frequency dependence.

An integrated resistor divider and external capacitor create a low-noise ADC reference without a buffer, cutting power, area, and DC error.

A shift-based gray code counter stores summed reset codes to cut counter area, reduce image noise, and support faster autofocus.

Switches equalize internal stack-gate nodes so differential comparator operation cancels kickback noise and improves ADC SNR.

By extracting echo features near the ADC, this case cuts optical detection data bandwidth and power while preserving useful signal fidelity.

A top-plate bootstrapped sampling circuit uses a voltage doubler and self-driven clocking to improve ADC bandwidth, linearity, and power use.

Transmission-period sampling adjusts receiver gain to suppress noise, remove bandpass filters, and shrink circuit area for pen signal detection.

Parallel signal and reference transistor paths slow short noise responses in a comparator stage, reducing chattering on slow waveforms.

A single EEPROM address terminal uses internal resistors, filtering, and ADC conversion to improve address recognition and cut board area.

Parallel capacitive channels with different capacitances are selected by signal magnitude to keep SNR stable across a wide dynamic range.

A cryogenic 3T bitcell topology improves write reliability at low temperatures while enabling low-power Boolean and convolutional in-memory computing.

A single-input comparator and ramp-based quantizer shrink image sensor footprint while preserving low-voltage ADC performance and reducing power.

Injected reference signals reveal channel delay differences after ADC, enabling digital time alignment without phase-matching cables.

Variable RF gain conditioning keeps antenna signals within ADC dynamic range, improving RFIC processing and reducing interference in 5G receivers.

Parallel variable resistors and ramp-generated control voltages give TIAs accurate, low-drift dB-linear gain across temperature and supply changes.

Selective TDD-aware skew calibration corrects phase mismatch between TI-ADC slices in two-carrier aggregation, reducing inter-carrier interference.

A configurable ADC circuit switches between high-speed and high-resolution modes to cut area and power across 2G, 3G, and 4G operation.

Digital square-wave mixing cuts channel count and fixed analog hardware, helping receivers adapt to changing multi-subband frequencies.

Current interpolation with TIA conversion cuts phase rotator power use while supporting higher-speed clock and data recovery links.

On-chip polynomial tuning computes ADC component values and maps them to registers, enabling dynamic bandwidth and center-frequency adjustment.

A 2-bit CMOS DAC and mirrored buffers generate adjustable PAM4 levels for Mach-Zehnder modulators while limiting distortion and parasitics.

Sub-carrier SNR drives multi-section ADC range selection to cut receiver current while keeping quantization error and signal quality in check.

Grouping similar PWM pulse widths into convergence values shrinks infrared signal data, speeding transmission and reducing storage space.

Parallel oversampling paths and noise shaping raise DAC bandwidth and resolution while reducing jitter, quantization noise, and mismatch errors.

Schottky-diode clamping limits OpAmp output to ADC rails, preventing overvoltage damage with low distortion and less circuit complexity.