Voltage-Controlled Delay Comparator for Faster ADC Decisions
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Solution Overview
Problem
Conventional high-speed analog-to-digital converters (ADCs) are slowed by the long time required for comparators to make decisions, introducing timing complexities due to the need to hold input signals for over 100ps, which affects the speed and efficiency of the conversion process.
Innovation Solution
A high-speed latch comparator with a voltage-controlled delay circuit that converts input voltage information into time information, using a delay circuit with transistors and inverters to generate differential delayed clock signals, allowing the comparator to operate faster and reduce timing complexities while maintaining accurate decision-making.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional comparators are used in high-speed ADCs, then the comparator can make decisions, but the decision time is long (over 100ps) which slows down the ADC conversion process
Solution Approach 1:
The delay circuit performs preliminary action by pre-delaying the clock signal before it reaches the comparator. This allows the comparator to operate on already-delayed signals, reducing the critical path timing requirements and enabling faster decision-making without sacrificing accuracy.
Solution Approach 2:
The delay circuit introduces dynamic timing control by adjusting the delay amount based on process, voltage, and temperature conditions. This dynamic adaptation allows the comparator to maintain optimal performance across varying operating conditions, achieving sub-25ps decision times while preserving conversion accuracy.
2Productivity
If the comparator decision time is reduced to increase ADC speed, then conversion efficiency improves, but timing complexities increase due to the need to hold input signals
Solution Approach 1:
The delay circuit extracts the timing control function from the main comparator operation. By separating the delay function into a dedicated circuit block, the timing complexities are isolated and managed independently, allowing the comparator to focus solely on accurate decision-making while the delay circuit handles timing adjustments.
Solution Approach 2:
The delay circuit acts as an intermediary between the clock signal and the comparator. It mediates the timing relationship by introducing controlled delays, thereby simplifying the overall timing control architecture and reducing the complexity of signal holding requirements in the ADC system.
3Measurement precision
If input signals are held for over 100ps to ensure accurate comparison, then decision accuracy is maintained, but the ADC speed is reduced
Solution Approach 1:
The delay circuit performs preliminary timing adjustment by pre-delaying the clock signal. This allows the comparator to make accurate decisions on signals that have already been properly timed, eliminating the need to hold input signals for extended periods while maintaining comparison accuracy.
Solution Approach 2:
The delay circuit replaces the mechanical signal holding approach with an electronic timing control mechanism. Instead of physically holding signals for over 100ps, the delay circuit uses electronic delay elements to achieve the same timing effect, thereby maintaining accuracy while enabling faster conversion speeds.
Data Source
Figure 1~4B
Figure 2
Figure 3
AI summary
A comparator (104) includes a pair of back-to-back negative-AND (NAND) gates (254/260/264 and 256/262/266) and a delay circuit (202, 204) coupled to the pair of back-to-back NAND gates (254/260/264 and 256/262/266). The delay circuit (202, 204) is configured to modulate a triggering clock signal by an input voltage to generate a delayed clock signal with a delay that is based on the input voltage. Each of the pair of back-to-back NAND gates (254/260/264 and 256/262/266) is configured to receive the delayed clock signal and generate a comparator output signal based on the delayed clock signal.