Single-Terminal EEPROM Address Circuit With ADC Noise Filtering
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional memory systems using EEPROMs face challenges in efficiently managing address recognition and noise interference due to the complexity of address terminal configurations, which can lead to erroneous recognition and increased board mounting area requirements.
Innovation Solution
The semiconductor integrated circuit device employs a pull-up resistor and a pull-down resistor with a filter circuit and AD converter configuration, including a resistor ladder circuit and chopper type comparators, to convert address terminal voltage into digital data, allowing for precise address setting and noise filtering, thereby simplifying the circuit and reducing terminal count.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple address terminals are used for EEPROM address recognition, then address identification capability is improved, but device complexity and board mounting area increase
Solution Approach 1:
The patent combines multiple address terminals into a single address terminal by integrating pull-up and pull-down resistors internally. The EEPROM model 24C02 uses one address terminal (A0) with internal resistance elements to generate multiple address states (000, 001, 010, 011, 100, 101, 110, 111), replacing the conventional approach that would require three separate address terminals.
Solution Approach 2:
The single address terminal serves multiple functions by working with internal pull-up and pull-down resistors to generate multiple address states. This multi-functional design allows one terminal to perform the work of multiple terminals, reducing device complexity while maintaining full address identification capability.
2Adaptability or versatility
If multiple address terminals are used for EEPROM address recognition, then address identification capability is improved, but board mounting area increases
Solution Approach 1:
The patent merges multiple address terminals into a single terminal configuration, reducing the number of connection points on the PCB. By using one address terminal with internal resistance elements instead of three separate terminals, the board mounting area is significantly reduced while maintaining the ability to address all 8 EEPROM devices in the system.
3Measurement precision
If conventional address terminal configuration is used, then address recognition is achieved, but noise interference increases causing erroneous recognition
Solution Approach 1:
The patent introduces internal pull-up and pull-down resistors as intermediary elements between the address terminal and the address recognition circuit. These resistance elements act as mediators that stabilize the voltage level at the address terminal, filtering out noise and preventing erroneous address recognition while maintaining accurate address identification.
4Measurement precision
If internal pull-up and pull-down resistors are implemented, then noise filtering and address precision are improved, but device complexity increases
Solution Approach 1:
The patent combines the pull-up resistor, pull-down resistor, and address recognition functionality into a single integrated circuit device. Rather than implementing these as separate external components, they are merged within the EEPROM chip itself, reducing overall system complexity while achieving precise address recognition with noise filtering.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enables precise address recognition, reduces noise interference, and minimizes board area by allowing for a single address terminal, enhancing the reliability and compactness of the memory system.
Implementation Method 1
a resistor ladder circuit configured to generate a plurality of reference voltages
Implementation Method 2
chopper type comparators configured to convert a voltage of the address terminal into digital data
Data Source
AI summary
A semiconductor integrated circuit device includes: a terminal; an internal resistor that is any one of a pull-up resistor configured so that a first end of the pull-up resistor is connected to the terminal and a first constant voltage is applied to a second end of the pull-up resistor, or a pull-down resistor configured so that a first end of the pull-down resistor is connected to the terminal and a ground voltage is applied to a second end of the pull-down resistor; and an AD converter configured so that a voltage of the terminal is converted into digital data having a number of bits of 2 or more.