Capacitor-Coupled Memory Bit Cell for Accurate In-Memory Multiply
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Solution Overview
Problem
Conventional computer systems face challenges in executing machine learning algorithms due to excessive power dissipation and poor performance from computation-intensive operations like multiply and accumulate operations, which are not well-suited to conventional hardware configurations.
Innovation Solution
Implementing a compute-memory circuit that uses capacitors in data storage cells to control the amount of charge coupled onto bit lines during multiplication operations, reducing variation and improving accuracy by employing in-memory computing techniques.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If conventional computer systems are used to execute machine learning algorithms with computation-intensive operations, then the system can perform general-purpose computing tasks, but excessive power dissipation and poor performance occur
Solution Approach 1:
The patent merges memory and computation functions into a single integrated structure. Memory cells store weight values while simultaneously performing multiplication operations with input data through controlled charge transfer. This eliminates the need to move data between separate memory and processing units, reducing energy consumption from data transfer while maintaining high computational throughput for machine learning workloads.
Solution Approach 2:
The patent replaces conventional transistor-based switching mechanisms with capacitor-based charge transfer mechanisms. Capacitors directly transfer charge representing computational results to bit lines, eliminating the need for complex transistor switching sequences. This substitution reduces power dissipation associated with transistor gate switching while enabling more efficient parallel computation operations.
2Measurement precision
If transistors are used to transfer charge onto bit lines during multiplication operations, then the circuit can perform computation, but voltage level variations increase and accuracy decreases
Solution Approach 1:
The patent replaces transistor-based charge transfer with direct capacitor-to-bit-line charge transfer. Capacitors maintain more stable voltage levels during charge transfer because they directly couple the stored charge to the bit line without the variable resistance and threshold voltage effects present in transistors. This results in reduced voltage level variations and improved computation accuracy.
Solution Approach 2:
The patent changes the fundamental parameter control mechanism from transistor gate voltage control to capacitor charge storage. By storing precise charge amounts on capacitors that represent weight values, the system achieves more stable and predictable charge transfer to bit lines. This parameter change from voltage-controlled (transistor) to charge-controlled (capacitor) operation reduces variability in voltage levels.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the accuracy and reduces power consumption in performing in-memory computations by minimizing voltage level variations on bit lines, thereby improving the performance of machine learning algorithms.
Implementation Method 1
A given compute data storage cell of a plurality of compute data storage cells includes a capacitor and is configured to store a corresponding bit of the weight value
Data Source
AI summary
A compute-memory circuit included in a computer system may include multiple compute data storage cells coupled to a compute bit line via respective capacitors. The compute data storage cells may store respective bits of a weight value. During a multiply operation, an operand may be used to generate a voltage level on a compute word line that is used to store respective amounts of charge on the capacitors, which are coupled to the compute bit line. The voltage on the compute bit line may be converted into multiple bits whose value is indicative of a product of the operand and the weight value.