Physical Quantity Detection Circuit With PLL-Based Digital Synchronous Mixing
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Solution Overview
Problem
Existing physical quantity detection devices face challenges with large circuit area and high power consumption due to the use of analog multipliers for synchronous detection, which also introduce noise and complexity.
Innovation Solution
A circuit device incorporating a phase-locked loop circuit to generate a digital sinusoidal wave signal phase-locked to a drive clock signal, an analog-to-digital conversion circuit, and a mixer for digital signal processing, eliminating the need for analog multipliers and reducing noise and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If an analog multiplier is used to multiply the frequency of a signal from the drive circuit, then synchronous detection can be performed, but the circuit area becomes large and power consumption increases
Solution Approach 1:
The patent replaces the analog multiplier (mechanical/electrical analog system) with a digital signal processing system consisting of a phase-locked loop circuit, A/D conversion circuit, and digital mixer. This substitution achieves the same frequency multiplication and synchronous detection function while significantly reducing circuit area and power consumption by using digital logic instead of analog components.
Solution Approach 2:
The patent changes the operating parameters by converting the detection signal from analog to digital domain through A/D conversion. This parameter change enables the use of digital signal processing techniques, fundamentally altering how frequency multiplication and synchronous detection are achieved, thereby reducing the physical circuit requirements.
2Measurement precision
If an analog multiplier is used for synchronous detection, then frequency multiplication can be achieved, but power consumption increases
Solution Approach 1:
The patent replaces the power-hungry analog multiplier with a digital signal processing system. The phase-locked loop circuit generates a digital sinusoidal wave signal, which is then mixed with the A/D converted detection signal in a digital mixer. This digital implementation consumes significantly less power while achieving the same synchronous detection function.
Solution Approach 2:
The patent creates a digital copy of the analog signal processing function. Instead of directly multiplying analog signals, it converts the detection signal to digital form and performs the multiplication operation in the digital domain, achieving the same result with lower power consumption.
3Measurement precision
If an analog multiplier is used, then synchronous detection is possible, but noise and circuit complexity increase
Solution Approach 1:
The patent replaces the complex analog multiplier circuit with a modular digital signal processing system. The phase-locked loop circuit, A/D conversion circuit, and digital mixer are distinct functional blocks that can be independently optimized and implemented, reducing overall circuit complexity while eliminating analog noise sources.
Solution Approach 2:
The patent segments the synchronous detection function into separate modular components: the phase-locked loop circuit for frequency synchronization, the A/D conversion circuit for signal digitization, and the digital mixer for signal multiplication. This segmentation reduces circuit complexity by allowing each component to be independently designed and optimized.
Data Source
AI summary
A circuit device includes a drive circuit configured to drive a physical quantity transducer, a phase-locked loop circuit configured to generate a digital sinusoidal wave signal phase-locked to a drive clock signal from the drive circuit, an analog-to-digital (A/D) conversion circuit configured to perform A/D conversion of a detection signal of the physical quantity transducer, and a mixer configured to perform a multiplication between the digital detection signal after the A/D conversion and the digital sinusoidal wave signal. The phase-locked loop circuit is configured to perform a phase comparison between the drive clock signal and the digital sinusoidal wave signal or a digital phase signal to generate the digital sinusoidal wave signal phase-locked to the drive clock signal.