Multi-Stage DTC Randomization for Fractional Spur Reduction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Fractional spurs in retimers used for high-speed data transmission, caused by fractional-N frequency synthesizers, limit the achievable bit error rate due to deterministic jitter from fractional spurs in multi-stage digitally controlled delay lines.
Innovation Solution
A circuit and method utilizing a digital to time converter with series-connected delay stages and an offset stage to generate random codes, reducing the probability of landing at mid-code positions and improving integrated nonlinearity, thereby enhancing linearity and reducing fractional spurs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If fractional-N frequency synthesizer is used to generate clock for TX, then lane speed flexibility is improved, but fractional spurs are generated causing deterministic jitter that limits bit error rate
Solution Approach 1:
The patent converts the harmful deterministic jitter from fractional spurs into beneficial random jitter by using a random delay generator. The random delay generator adds random time delays to the data signal, which transforms the periodic deterministic jitter into non-periodic random jitter that can be filtered out by the receiver's timing recovery circuitry, thereby improving bit error rate performance while maintaining the flexibility of fractional-N frequency synthesis
2Manufacturing precision
If multi-stage digitally controlled delay line is used to correct timing errors, then timing margin is improved, but integrated nonlinearity at mid-code position causes fractional spurs
Solution Approach 1:
The patent segments the delay line into multiple stages with different code ranges. Each stage handles a specific range of delay values, and the stages are cascaded together. This segmentation prevents any single stage from operating continuously at its mid-code position, thereby reducing the integrated nonlinearity that causes fractional spurs while maintaining the overall timing correction capability
Solution Approach 2:
The patent introduces dynamic randomization by adding a random delay generator that continuously varies the delay applied to the data signal. This dynamic adjustment ensures that the delay line does not settle into fixed mid-code positions, thereby reducing the deterministic nonlinearity that generates fractional spurs while maintaining timing margin
Data Source
AI summary
A circuit or reducing fractional spurs comprises a digital to time converter (DTC) comprising multiple delay stages electrically coupled to one another in series, configured such that each delay stage is binary switched till the code exceeds cell range and then it is fully turned ON, and thereafter it is moved to the next stage, each delay stage comprising a digitally controlled delay line (DCDL) having code-dependent integrated nonlinearity (INL), with the maximal value of the INL occuring at a mid-code position; and an offset stage comprising the DCDL electrically coupled to the DTC in series, configured to generate random codes for each required time delay of the DTC to ensure the probability of landing at the mid-code position is reduced and landing point is kept as far away as possible from the mid-code position for every required time delay, thereby improving the INL and the fractional spurs.