CDTA Buffer Circuit With Current Feedback for High-Speed ADCs
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Solution Overview
Problem
Modern high-speed Analog-to-Digital Converters (ADCs) face challenges in achieving sub-picosecond timing resolution and high bandwidth due to RF buffer limitations, such as slew-rate and bandwidth constraints, which affect gain and timing-skew performance while increasing power consumption.
Innovation Solution
A buffer circuit utilizing a Current Differencing Transconductance Amplifier (CDTA) with wideband source follower circuits and current-feedback architecture, providing high bandwidth and reduced sensitivity to parasitic capacitances, and enabling superior robustness against Electrical OverStress.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional RF buffers are used in high-speed ADCs, then the basic buffering function is provided, but bandwidth and slew-rate limitations occur which degrade timing resolution and gain performance
Solution Approach 1:
The patent replaces conventional voltage-mode RF buffer architecture with a current-mode buffer architecture using CDTA. This substitution fundamentally changes the operating mechanism from voltage-based to current-based signal processing, enabling superior bandwidth and slew-rate performance while maintaining timing resolution. The current-mode operation allows the buffer to drive the ADC input without the bandwidth limitations that plague voltage-mode buffers at high frequencies.
2Power
If RF buffer gain is increased to improve signal level, then gain performance improves, but power consumption increases significantly
Solution Approach 1:
The patent changes the fundamental operating parameters of the buffer by adopting current-mode operation with CDTA. Instead of increasing voltage gain which requires more power, the invention uses current amplification capabilities of the CDTA to achieve the desired signal level at the ADC input. The current-mode architecture provides gain without the quadratic power increase typical of voltage-mode buffers, thereby resolving the contradiction between gain and power consumption.
3Reliability
If conventional voltage-mode buffers are used, then the buffering function is achieved, but sensitivity to parasitic capacitances degrades performance
Solution Approach 1:
The patent substitutes voltage-mode buffering with current-mode buffering using CDTA. In current-mode operation, signals are processed as currents rather than voltages, which fundamentally changes the interaction with parasitic capacitances. The CDTA's current-output特性 means that parasitic capacitances at the output node have minimal impact on signal integrity, as the current signal is less susceptible to capacitive loading effects compared to voltage signals. This substitution provides inherent robustness against parasitic capacitances.
4Productivity
If time-interleaved ADC architecture is used to increase throughput, then aggregate sample rate increases, but timing skew and gain mismatches between sub-ADCs degrade performance
Solution Approach 1:
The patent employs a universal current-mode buffer architecture that can serve multiple sub-ADCs in a time-interleaved configuration. The CDTA-based buffer provides consistent performance characteristics across all channels, ensuring uniform bandwidth, gain, and timing characteristics. This universality allows the buffer to maintain precise timing alignment and matched gain across multiple parallel paths, thereby supporting high throughput time-interleaved operation without suffering from the timing skew and gain mismatch problems that plague conventional separate buffer implementations for each sub-ADC.
Data Source
AI summary
A buffer circuit is provided. The buffer circuit includes a Current Differencing Transconductance Amplifier (CDTA) comprising a first input node and a second input node each configured to receive a respective one of a first signal and a second signal. The buffer circuit further includes a first source follower circuit coupled to a first output node of the CDTA and configured to generate a first buffer output signal based on a first output signal of the CDTA. Additionally, the buffer circuit includes a second source follower circuit coupled to a second output node of the CDTA and configured to generate a second buffer output signal based on a second output signal of the CDTA. The buffer circuit further includes a first feedback path comprising at least one of a first resistive element and a first capacitive element. The first feedback path couples an output node of the first source follower circuit to the first input node of the CDTA. In addition, the buffer circuit includes a second feedback path comprising at least one of a second resistive element and a second capacitive element. The second feedback path couples an output node of the second source follower circuit to the second input node of the CDTA.