Cryogenic 3T CIMC Macros for Reliable Writes and Boolean Computing
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Solution Overview
Problem
Existing cryogenic enhanced dynamic random access memory (eDRAM) is not optimal for reliable write operations at cryogenic temperatures, and its bitcell topology needs to be redesigned to meet the requirements of different computing operations, particularly in energy-efficient Boolean logic and convolutional operations.
Innovation Solution
The design of an energy-efficient cryogenic-in-memory-computing (CIMC) accelerator using cryogenic 3T (C3T) macros, which include a C3T array with bitcells, a digital timing sequence converter, and a sense amplifier, enabling efficient charging and discharging on read bit lines, and adaptive reconfigurable sense amplifiers for Boolean and convolutional operations, along with a cryogenically optimized flash analog-to-digital converter.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If existing cryogenic eDRAM is used, then memory storage is achieved, but write operation reliability deteriorates at cryogenic temperatures
Solution Approach 1:
The patent changes the bitcell topology from conventional 6T to a specialized 3T design optimized for cryogenic temperatures. This structural parameter change enables reliable write operations at cryogenic temperatures by using a pull-up transistor configuration that maintains proper voltage levels during write operations, overcoming the reliability issues of standard eDRAM at low temperatures.
Solution Approach 2:
The patent implements dynamic control mechanisms including word line voltage boosting and adaptive timing sequences that adjust operation parameters based on temperature conditions. The sense amplifier is dynamically configured with adjustable reference voltages to maintain optimal sensitivity across varying cryogenic temperatures, ensuring reliable write and read operations.
2Use of energy by moving object
If cryogenic computing architecture is implemented, then energy efficiency is improved, but computational versatility deteriorates due to limited operation types
Solution Approach 1:
The patent designs a universal C3T bitcell that can perform multiple computational functions including Boolean logic operations (AND, OR, NOT), convolutional operations, and standard memory operations. The same hardware structure supports different computing modes by adjusting control signals and timing sequences, eliminating the need for separate specialized circuits for each operation type.
Solution Approach 2:
The patent implements a reconfigurable architecture where the computational mode is dynamically selected through control signals. The system can switch between Boolean logic mode, convolutional mode, and memory mode by adjusting word line activation sequences and sense amplifier configuration, providing computational versatility while maintaining energy-efficient cryogenic operation.
3Reliability
If C3T bitcell topology is used, then write operation reliability is improved, but device complexity increases compared to conventional eDRAM
Solution Approach 1:
The patent applies local quality optimization by placing the pull-up transistor specifically at the bit line intersection point where it is most needed for write operation reliability. This localized structural modification provides the necessary voltage boosting only where required, rather than complicating the entire memory array structure, thus balancing reliability improvement with acceptable device complexity.
4Use of energy by moving object
If cryogenic computing is implemented, then cooling cost is reduced through high energy efficiency, but manufacturing precision requirements worsen due to cryogenic environment constraints
Solution Approach 1:
The patent optimizes transistor sizing parameters specifically for cryogenic operation, adjusting width-to-length ratios to compensate for changed carrier mobility characteristics at low temperatures. The pull-up transistor is sized to provide appropriate pull-up strength without requiring excessive precision in fabrication, making the design more tolerant of manufacturing variations while maintaining reliability at cryogenic temperatures.
Data Source
AI summary
An energy-efficient cryogenic-in-memory-computing (CIMC) accelerator includes cryogenic 3T (C3T) macros. Each of the C3T macros comprises a C3T array containing M rows×N columns of bitcells. An input signal is converted into a timing sequence signal of a corresponding pulse width by using a digital timing sequence converter array. A C3T bitcell of a corresponding row in the C3T macro is controlled to perform charging and discharging on a read bit line (RBL) of a corresponding column. A voltage on the RBL of the corresponding column is sampled by a sense amplifier configured in each C3T macro to obtain a final result. With adaptive reference voltage configuration and storage on the chip, this design can achieve fast and low-power boolean/convolutional computing.