Parallel Oversampling DAC Architecture for High-Rate Resolution

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Solution Overview

Problem

Conventional digital-to-analog converters face limitations in high-resolution conversion at very high sampling rates due to issues like quantization noise, sampling jitter, thermal noise, and component mismatches, which restrict their instantaneous bandwidth and resolution.

Innovation Solution

The proposed solution involves a discrete-time noise-shaping/quantization circuit with multiple parallel processing paths, a multiplexer, a multi-bit-to-variable-level signal converter, and an analog bandpass filter, which operates at a subsampling rate lower than the input signal sampling rate, allowing for improved noise frequency response and higher resolution.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If conventional DACs operate at very high sampling rates, then instantaneous bandwidth is improved, but resolution and conversion accuracy deteriorate due to quantization noise, sampling jitter, and thermal noise

Engineering Contradiction:
Improvesampling rateVSAvoidconversion resolution
Core Design Contradiction:
SpeedVSMeasurement precision

Solution Approach 1:

The patent divides the high-rate digital input signal into multiple parallel lower-rate processing paths using a demultiplexer. Each path processes a subset of the signal at a reduced sampling rate, which reduces quantization noise and thermal noise effects. The parallel paths are then recombined to reconstruct the full-rate output signal, achieving high instantaneous bandwidth while maintaining high conversion resolution.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces an intermediate parallel processing stage with multiple demultiplexed paths that operate at subsampling rates. This intermediary structure allows noise reduction in each parallel path while maintaining the overall high sampling rate capability through recombination, effectively decoupling the bandwidth and resolution requirements.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Measurement precision

If conventional DACs increase conversion resolution, then accuracy is improved, but instantaneous bandwidth is limited by the Nyquist criterion and component mismatches

Engineering Contradiction:
Improveconversion resolutionVSAvoidinstantaneous bandwidth
Core Design Contradiction:
Measurement precisionVSSpeed

Solution Approach 1:

The patent segments the high-bandwidth signal conversion task into multiple parallel lower-bandwidth conversion paths. Each parallel converter operates at a reduced sampling rate, allowing higher resolution conversion without being limited by the Nyquist criterion at the full sampling rate. The parallel outputs are recombined to achieve the full instantaneous bandwidth with high resolution.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent transitions from a single-dimensional high-rate conversion approach to a multi-dimensional parallel processing architecture. By adding the dimension of parallel processing paths, the system achieves both high instantaneous bandwidth (through the number of parallel paths) and high conversion resolution (through lower individual path rates), effectively trading structural complexity for performance in both dimensions.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

3Measurement precision

If conventional DACs use fine granularity quantization, then resolution is improved, but quantization noise and rounding errors increase

Engineering Contradiction:
Improvequantization resolutionVSAvoidquantization noise
Core Design Contradiction:
Measurement precisionVSObject-generated harmful factors

Solution Approach 1:

The patent segments the quantization process into multiple parallel coarse quantization paths, each operating at a lower sampling rate. This segmentation reduces the quantization noise burden on each individual path while maintaining fine effective resolution through the parallel combination. The demultiplexer distributes the input signal to parallel quantizers that each handle a portion of the signal with reduced quantization noise.

Inventive Principle:
Principle #1Segmentation

4Speed

If conventional DACs operate at high sampling rates, then bandwidth is improved, but sampling jitter and timing errors increase

Engineering Contradiction:
Improvesampling rateVSAvoidtiming accuracy
Core Design Contradiction:
SpeedVSReliability

Solution Approach 1:

The patent segments the high-rate sampling operation into multiple parallel lower-rate sampling paths. Each parallel path operates at a reduced sampling rate, which reduces sampling jitter and timing errors in each individual path. The demultiplexer and subsequent recombination structure maintains the overall high instantaneous bandwidth while improving timing accuracy through the parallel lower-rate operation.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS9509331B1Conversion of a discrete-time quantized signal into a continuous-time, continuously variable signal
Publication Date: 2016.11.29 PAGNANELLI FAMILY TRUST
  • US9509331B1 patent drawing
  • US9509331B1 patent drawing
  • US9509331B1 patent drawing

AI summary

Provided are, among other things, systems, apparatuses, methods and techniques for converting a discrete-time quantized signal into a continuous-time, continuously variable signal. An exemplary converter preferably includes: (1) multiple oversampling converters, each processing a different frequency band, operated in parallel; (2) multirate (i.e., polyphase) delta-sigma modulators (preferably second-order or higher); (3) multi-bit quantizers; (4) multi-bit-to-variable-level signal converters, such as resistor ladder networks or current source networks; (5) adaptive nonlinear, bit-mapping to compensate for mismatches in the multi-bit-to-variable-level signal converters (e.g., by mimicking such mismatches and then shifting the resulting noise to a frequently range where it will be filtered out by a corresponding bandpass (reconstruction) filter); (6) multi-band (e.g., programmable noise-transfer-function response) bandpass delta-sigma modulators; and/or (7) a digital pre-distortion linearizer (DPL) for canceling noise and distortion introduced by an analog signal bandpass (reconstruction) filter bank.