Boron-Doped Capping Tier for Corrosion-Resistant 3D NAND Stacks
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Solution Overview
Problem
Conventional methods of forming 3D NAND Flash memory devices result in undesirable damage to features, leading to performance, reliability, and durability issues due to damage to underlying structures during the replacement gate process.
Innovation Solution
The use of boron-doped semiconductor material as a capping tier in microelectronic devices, which mitigates damage during processing by enhancing etch resistance and processing efficiency, and includes a method of forming trenches and dielectric liners to protect underlying features.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional replacement gate processing is used to form stack structures, then memory device integration and density can be increased, but underlying features suffer from corrosion-based damage leading to reduced reliability and durability
Solution Approach 1:
A boron-doped semiconductor capping tier is introduced as an intermediary protective layer between the etchant environment and the underlying features. This capping tier acts as a mediator that resists corrosion during replacement gate processing, preventing damage to the underlying memory structures while allowing the processing to proceed for achieving high integration and density.
Solution Approach 2:
The boron-doped semiconductor capping tier is formed in advance before the replacement gate processing occurs. This preliminary protective layer is prepared beforehand to shield the underlying features from corrosion damage that would otherwise occur during the subsequent etching and processing steps required for achieving high memory device integration.
2Quantity of substance
If feature packing densities are increased to improve memory density, then more memory cells can be packed in a given area, but margins for formation errors decrease leading to increased damage and defects
Solution Approach 1:
The boron-doped semiconductor capping tier serves as a cushioning protective layer formed beforehand to absorb and mitigate the effects of formation errors and processing variations. When feature packing densities are increased, this pre-formed capping tier provides a buffer that prevents minor formation errors from propagating into defects that would compromise memory device functionality.
3Adaptability or versatility
If sacrificial structures are replaced with conductive structures in preliminary stack structures, then vertical memory array functionality is achieved, but underlying materials and structures suffer damage
Solution Approach 1:
The boron-doped semiconductor capping tier acts as a protective intermediary layer that remains in place during the replacement gate process. This intermediary layer shields the underlying materials and structures from damage caused by the removal and replacement of sacrificial structures, while still allowing the vertical memory array functionality to be achieved through the replacement process.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The boron-doped semiconductor material effectively prevents corrosion-based damage and enhances processing efficiency, resulting in improved reliability and durability of the microelectronic devices.
Implementation Method 1
The boron-doped semiconductor material may have enhanced etch resistance relative to the sacrificial material of the lateral contact tier
Data Source
AI summary
A microelectronic device includes a boron-doped semiconductor material, a stack structure, slot structures, and cell pillar structures. The boron-doped semiconductor material is vertically above a lateral contact material. The stack structure is vertically above the boron-doped semiconductor material and includes blocks horizontally extending in parallel in a first direction and individually having tiers respectively including conductive material and insulative material vertically neighboring the conductive material. The slot structures vertically extend through the stack structure, the boron-doped semiconductor material, and the lateral contact material. The slot structures horizontally alternate with the blocks of the stack structure in a second direction orthogonal to the first direction. The cell pillar structures respectively include semiconductor material in contact with the lateral contact material and vertically extending through each of the lateral contact material, the boron-doped semiconductor material, and the stack structure. Related methods and memory devices are also described.