Boron-Rich Interface Layer for Semiconductor Contact Resistance

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Solution Overview

Problem

The complexity and increased resistance issues between epitaxial structures and contact plugs or substrates in semiconductor devices hinder efficient electrical performance.

Innovation Solution

A semiconductor device with a boron-rich interface layer encasing the epitaxial source/drain structure, reducing resistance by incorporating boron ions between the epitaxial source/drain and other elements like contact plugs or substrates.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If an epitaxial structure is used to improve device performance, then carrier mobility and device speed are improved, but resistance between the epitaxial structure and contact plugs or substrate increases

Engineering Contradiction:
Improvedevice speedVSAvoidcontact resistance
Core Design Contradiction:
SpeedVSReliability

Solution Approach 1:

A boron-rich interface layer is introduced as an intermediary between the epitaxial source/drain structure and the substrate or contact plugs. This interface layer has high boron concentration that reduces contact resistance by facilitating charge carrier transport across the interface, while the epitaxial structure maintains its strain-induced high carrier mobility in the channel region.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The boron concentration is localized specifically at the interface regions between the epitaxial structure and surrounding elements (substrate and contact plugs), rather than being uniformly distributed. This creates a high boron concentration zone precisely where contact resistance needs to be reduced, while preserving the low-doped properties of the bulk epitaxial structure that provide strain benefits.

Inventive Principle:
Principle #3Local quality

2Speed

If an epitaxial structure is used to improve device performance, then carrier mobility is improved, but fabrication complexity increases

Engineering Contradiction:
Improvecarrier mobilityVSAvoidfabrication complexity
Core Design Contradiction:
SpeedVSDevice complexity

Solution Approach 1:

The formation of the boron-rich interface layer is combined with existing fabrication steps such as ion implantation or in-situ doping during epitaxial growth. By merging the interface layer creation with already-required process steps, the overall fabrication complexity is minimized while achieving the dual benefits of high carrier mobility and low contact resistance.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The boron-rich interface layer is formed preliminarily before contact plug formation or during the epitaxial growth stage itself. This preliminary action ensures that the low-resistance interface is already in place before subsequent processing steps, eliminating the need for additional dedicated steps to reduce contact resistance later in the fabrication process.

Inventive Principle:
Principle #10Preliminary action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The boron-rich interface layer effectively reduces contact resistance by 10%-18%, enhancing the electrical performance of semiconductor devices.

Implementation Method 1

the boron ions in the boron-rich interface layer efficaciously reduce resistance between the epitaxial source/drain structure and the element such as the contact plugs or the substrate

Methodology Applied
Scientific EffectIon implantation: Ion Implantation

Implementation Method 2

the prior art usually forms an epitaxial layer such as a silicon germanium (hereinafter abbreviated as SiGe) layer in a single crystal substrate by performing a selective epitaxial growth (hereinafter abbreviated as SEG) method

Methodology Applied
Scientific EffectEpitaxy: Epitaxy

Implementation Method 3

Because the lattice constant of the epitaxial SiGe layer is larger than that of the silicon substrate, a strain stress is generated to the channel region of the metal-oxide semiconductor (hereinafter abbreviated as MOS) transistor device

Methodology Applied
Scientific EffectStrain stress:

Data Source

PatentUS9397214B1Semiconductor device
Publication Date: 2016.07.19 STELLAR SEMICONDUCTOR JAPAN GK
  • US9397214B1 patent drawing
  • US9397214B1 patent drawing
  • US9397214B1 patent drawing

AI summary

A semiconductor device is provided includes a substrate, a gate structure formed on the substrate, an epitaxial source/drain structure respectively formed at two sides of the gate structure, and a boron-rich interface layer. The boron-rich interface layer includes a bottom-and-sidewall portion and a top portion, and the epitaxial source/drain structure is enclosed by the bottom-and-sidewall portion and the top portion.