Bottom Dielectric Structure for Lower Gate-Drain Capacitance
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Solution Overview
Problem
Conventional multi-gate devices, such as FinFETs and MBC transistors, face challenges with increased gate-drain capacitance (Cgd) and leakage paths due to epitaxial source/drain features extending below the gate structure and stray dopants in the bulk substrate, which affect performance, especially in high-frequency applications.
Innovation Solution
A bottom dielectric layer is introduced by forming a bottom sacrificial layer and capping layer on a substrate, patterning and replacing it with a dielectric feature, and forming epitaxial source/drain features in two stages to reduce gate-drain capacitance and leakage, using methods like molecular beam epitaxy and chemical vapor deposition.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multi-gate devices are used to improve gate control and reduce off-state current, then device performance is improved, but gate-drain capacitance increases and becomes critical to device performance
Solution Approach 1:
The source/drain region is segmented into multiple parts: a first source/drain region at the channel level, a second source/drain region extending below the gate structure, and a third source/drain region filling the trench. This segmentation allows each region to serve specific functions - the first region provides gate control, while the second and third regions are optimized to reduce capacitance and leakage separately.
Solution Approach 2:
Different regions of the source/drain structure are given different properties: the first source/drain region has properties optimized for gate control, the second region extends below the gate to reduce capacitance, and the third region fills the trench to eliminate leakage paths. Each local region has tailored characteristics to address specific performance requirements.
2Reliability
If epitaxial source/drain features extend below the gate structure to reduce short-channel effects, then device control is improved, but gate-drain capacitance and leakage paths increase
Solution Approach 1:
The harmful leakage paths are extracted and eliminated by filling the trench with dielectric material. The second source/drain region that extends below the gate is isolated from the substrate by removing or replacing the bottom sacrificial layer with dielectric material, thereby taking out the leakage pathway while preserving the beneficial capacitance-reducing geometry.
Solution Approach 2:
A dielectric material is introduced as an intermediary between the second source/drain region and the substrate. This intermediary layer blocks the leakage current path while allowing the second source/drain region to maintain its position for capacitance reduction, effectively mediating between the conflicting requirements.
3Productivity
If spacing between gate structures and source/drain features is reduced to increase functional density, then production efficiency is improved, but gate-drain capacitance becomes more critical
Solution Approach 1:
The source/drain structure is extended into the vertical dimension below the gate structure. The second source/drain region projects downward into the trench, utilizing the third dimension to reduce capacitance without requiring increased horizontal spacing, thereby maintaining high functional density while mitigating capacitance effects.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces gate-drain capacitance and leakage, enhancing the performance of multi-gate transistors by maintaining structural integrity and minimizing capacitive and conductive interference.
Implementation Method 1
the bottom sacrificial feature is replaced with a bottom dielectric feature
Implementation Method 2
forming epitaxial source/drain features in two stages to reduce gate-drain capacitance and leakage, using methods like molecular beam epitaxy and chemical vapor deposition
Data Source
AI summary
A semiconductor device according to the present disclosure includes a bottom dielectric feature on a substrate, a plurality of channel members directly over the bottom dielectric feature, a gate structure wrapping around each of the plurality of channel members, two first epitaxial features sandwiching the bottom dielectric feature along a first direction, and two second epitaxial features sandwiching the plurality of channel members along the first direction.