Bottom Electrode Via Barrier Layout to Prevent Memory Shorts

Resolve Bottlenecks,
Find Innovative SolutionsGenerate Solutions

Solution Overview

Problem

The existing manufacturing methods for memory devices often result in electrical shorting due to re-deposition of conductive materials during the etching process, which compromises the reliability of the memory devices in reading, writing, and storing data.

Innovation Solution

A method is introduced where the bottom electrode via (BEVA) is made narrower to prevent re-deposition of metallic by-products on the sidewalls of the data storage structure, and a low resistivity metal is used between the BEVA and the underlying metal interconnect to compensate for the increased resistance, ensuring reliable operation without electrical shorts.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a wider bottom electrode via is used, then via resistance is reduced, but the risk of electrical shorting due to re-deposition of conductive material increases

Engineering Contradiction:

Improveelectrical shorting preventionVSAvoidre-deposition of conductive material

Core Design Contradiction:

ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The patent extracts the conductive material from the BEVA structure by using a narrow via width that prevents re-deposition during etching, separating the via function from the conductive material deposition process

Inventive Principle:

Principle #2Taking out (Extraction)

Solution Approach 2:

The patent changes the width parameter of the bottom electrode via to a narrower dimension, which prevents re-deposition of conductive material on the data storage structure sidewalls during etching, thereby eliminating electrical shorting while maintaining acceptable via resistance

Inventive Principle:

Principle #35Parameter changes

2Reliability

If a narrower bottom electrode via is used, then electrical shorting is prevented, but via resistance increases

Engineering Contradiction:

Improveelectrical shorting preventionVSAvoidvia resistance

Core Design Contradiction:

ReliabilityVSObject-affected harmful factors

Solution Approach 1:

Inventive Principle:

Principle #35Parameter changes

Solution Approach 2:

The patent uses a composite structure combining the narrow BEVA with a low resistivity metal layer to achieve both shorting prevention and acceptable electrical conductivity

Inventive Principle:

Principle #40Composite materials

3Object-affected harmful factors

If a low resistivity metal is added between BEVA and metal interconnect, then via resistance is reduced, but manufacturing complexity increases

Engineering Contradiction:

Improvevia resistanceVSAvoidmanufacturing process complexity

Core Design Contradiction:

Object-affected harmful factorsVSDevice complexity

Solution Approach 1:

The patent changes the material property (resistivity) by introducing a low resistivity metal layer, which reduces via resistance while the narrow via width design maintains simplicity in preventing re-deposition

Inventive Principle:

Principle #35Parameter changes

Solution Approach 2:

The patent introduces a low resistivity metal as an intermediary layer between the BEVA and the metal interconnect to reduce contact resistance, serving as a mediator that improves electrical conductivity without complicating the overall structure

Inventive Principle:

Principle #24Intermediary (Mediator)

Data Source

PatentUS20230371397A1Bottom electrode via and conductive barrier design to eliminate electrical short in memory devices

Publication Date: 2023.11.16 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD

AI summary

In some embodiments, the present disclosure relates to an integrated chip (IC), including a bottom electrode overlying an interconnect structure disposed within a lower inter-level dielectric (ILD) layer, a top electrode over the bottom electrode, a data storage structure between the top electrode from the bottom electrode, a conductive barrier layer overlying the interconnect structure, and a bottom electrode via (BEVA) vertically separating and contacting a bottom surface of the bottom electrode and a top surface of the conductive barrier layer. A maximum width of the BEVA is less than a width of the data storage structure.