Boundary Cell Layout for TSV Keep-Out Zone ESD Protection

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Solution Overview

Problem

The miniaturization of integrated circuits poses challenges in design and manufacturing, particularly in ensuring adequate space for through silicon vias (TSVs) and electrostatic discharge (ESD) protection while maintaining functional circuit cells, as existing designs often occupy valuable space that could be used for functional circuits.

Innovation Solution

Implementing boundary cells adjacent to keep-out zones that accommodate TSVs and ESD protection circuits, allowing for enlarged gate-conductor areas to protect MOS transistors from electrostatic discharges, thereby freeing up space for functional circuit cells by positioning ESD protection circuits outside the areas between adjacent rectangular keep-out zones.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If ESD protection circuits are placed in the areas between adjacent keep-out zones, then ESD protection is provided, but valuable space is occupied that could be used for functional circuit cells

Engineering Contradiction:

ImproveESD protectionVSAvoidspace for functional circuit cells

Core Design Contradiction:

ReliabilityVSArea of stationary object

Solution Approach 1:

The ESD protection circuits are extracted from the areas between keep-out zones and relocated to boundary cells adjacent to the keep-out zones. This extraction removes the harmful occupation of valuable functional space while preserving the ESD protection function in a more appropriate location.

Inventive Principle:

Principle #2Taking out (Extraction)

Solution Approach 2:

The layout transitions from a two-dimensional placement where ESD circuits occupy horizontal space between keep-out zones to a boundary-based arrangement where ESD circuits are positioned along the perimeters of keep-out zones. This dimensional reorganization optimizes space utilization by confining ESD circuits to boundary regions.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

2Reliability

If the gate-conductor area is enlarged to protect MOS transistors from electrostatic discharges, then ESD protection capability is improved, but device area increases

Engineering Contradiction:

Improveprotection against electrostatic dischargesVSAvoiddevice area

Core Design Contradiction:

ReliabilityVSArea of stationary object

Solution Approach 1:

The enlarged gate-conductor area is applied locally only to the boundary cells containing ESD protection circuits, rather than uniformly across all circuit cells. This localized application provides enhanced ESD protection where needed while minimizing the overall area impact on the device.

Inventive Principle:

Principle #3Local quality

Data Source

PatentUS20250357385A1Method of fabricating device having boundary cells adjacent to keep-out zones

Publication Date: 2025.11.20 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD

AI summary

A method of fabricating an IC includes: forming first and second arrays of active-region structures extending between first and second vertical zone-boundaries, the first vertical zone-boundary being a boundary of a first keep-out zone, and the second vertical zone-boundary being a boundary of a second keep-out zone; forming first-side boundary cells aligned with the first vertical zone-boundary, including: forming a first-side boundary cell that includes: a first ESD device region including a first ESD protection circuit; and a first pick-up region; and forming second-side boundary cells aligned with the second vertical zone-boundary, including: forming a second-side boundary cell that includes: a second ESD device region including a second ESD protection circuit.