Boundary Gate Isolation in 3D-Stacked Semiconductors
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Solution Overview
Problem
The manufacturing complexity of 3D-stacked semiconductor devices is heightened by the need for high-aspect-ratio structural elements, particularly the diffusion break structure, which requires deep etching and complex formation steps.
Innovation Solution
A 3D-stacked semiconductor device design that employs reverse-biased gate structures as diffusion break structures, eliminating the need for traditional diffusion break structures by using existing gate structures to electrically isolate active regions, thereby simplifying the manufacturing process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional diffusion break structures are used for electrical isolation, then effective isolation is achieved, but manufacturing complexity increases due to deep etching and insulation deposition
Solution Approach 1:
The patent merges the function of the gate structure with the diffusion break function. The gate structure is extended into the active region and configured to provide electrical isolation between adjacent transistors, combining two previously separate functions (gate control and diffusion break) into a single integrated structure, thereby eliminating the need for separate deep etching and insulation deposition steps
Solution Approach 2:
The gate structure is designed to serve multiple functions: it provides gate control for the transistor, acts as a diffusion break for electrical isolation between adjacent active regions, and serves as a structural element in the 3D-stacked configuration. This multi-functionality reduces the number of separate components and manufacturing steps required
2Reliability
If traditional diffusion break structures are formed with deep etching, then electrical isolation is achieved, but manufacturing steps increase
Solution Approach 1:
The patent combines the gate structure formation process with the diffusion break formation process. The gate structure is extended into the active region during the same manufacturing steps used to create the gate, eliminating the need for separate deep etching and insulation deposition steps that would otherwise be required to create traditional diffusion break structures
Solution Approach 2:
The patent extracts the diffusion break function from the traditional separate insulation structure and integrates it into the gate structure itself. By removing the need for a distinct diffusion break structure and incorporating its isolating function into the gate, the manufacturing process is simplified while maintaining effective electrical isolation
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach simplifies the manufacturing process by eliminating the need for high-aspect-ratio deep etching and insulation deposition, enhancing device density and reducing manufacturing complexity while maintaining effective electrical isolation.
Implementation Method 1
at least one of the lower boundary gate structure and the upper boundary gate structure is reverse-biased to electrically isolate the lower-1st active sub-region from the lower-2nd active sub-region, and/or electrically isolate the upper-1st active sub-region from the upper-2nd active sub-region
Data Source
AI summary
Provided is a three-dimensional stacked (3D-stacked) semiconductor device which includes: a lower active region divided into a lower-1st active sub-region and a lower-2nd active sub-region by at least one lower boundary gate structure; and an upper active region, above the lower active region, divided into an upper-1st active sub-region and an upper-2nd active sub-region by at least one upper boundary gate structure, wherein at least one of the lower boundary gate structure and the upper boundary gate structure is reverse-biased to electrically isolate the lower-1st active sub-region from the lower-2nd active sub-region, and/or electrically isolate the upper-1st active sub-region from the upper-2nd active sub-region