Boundary Scan Cell Built-In Self-Test for I/O Characterization
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Solution Overview
Problem
Existing methods for input/output characterization of integrated circuits are inefficient and require external equipment, lacking a cost-effective and efficient built-in solution for testing interconnects and functionality, especially in packaged ICs.
Innovation Solution
A system and method utilizing boundary scan cells with test logic, initialization logic, and a clock shaping system within the IC to provide a test completion signal and adjust the clock signal's edge for efficient at-speed testing, enabling built-in self-test and characterization without external test equipment.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If external test equipment is used for I/O characterization, then measurement capability is provided, but device complexity and manufacturing cost increase
Solution Approach 1:
The boundary scan cell is configured to perform self-testing through built-in logic that automatically captures and compares output states without requiring external test equipment. The cell services its own testing needs by using internal storage elements and comparison logic to characterize I/O behavior.
Solution Approach 2:
The testing functionality is extracted from external test equipment and embedded directly into the boundary scan cell structure. The test logic, storage elements, and comparison functions are integrated within the IC, removing the need for external characterization equipment.
2Productivity
If traditional boundary scan cells are used, then interconnect testing is enabled, but testing speed and efficiency are limited
Solution Approach 1:
The output state is captured and stored in the first storage element before comparison is performed. This preliminary capture action allows the test to proceed asynchronously, eliminating waiting time and enabling faster test cycles while maintaining complete characterization capability.
3Reliability
If built-in test logic is added to boundary scan cells, then testing capability is improved, but circuit complexity increases
Solution Approach 1:
The boundary scan cell structure is enhanced to perform multiple functions: normal signal passing, output capture, state comparison, and self-testing. By making the cell universal and multi-functional, additional testing capabilities are integrated without requiring separate dedicated test circuits, thus limiting the increase in overall complexity.
Data Source
AI summary
A test system in an integrated circuit includes at least one boundary scan cell. The boundary scan cell includes a first storage element and a second storage element connected in series with the first storage element. The boundary scan cell also includes test logic configured to provide a test completion signal indicative of completion of a respective test based on a comparison of an output of the first storage element relative to test value (TVALUE). The output of the first storage element is provided to the input of the second storage element unchanged during a first operating state and, depending on the test completion signal, an inverted version of the output of the first storage element can be provided to the input of the second storage element during a second operating state. A bi-directional element is connected to receive the output of the second storage element and to feed the output of the second storage element back to an input of the first storage element.