Branch Prediction Circuit Back-Invalidation for Accurate Instruction Fetch
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Solution Overview
Problem
Existing branch prediction methods in processors lead to idle cycles due to incorrect prediction of target instructions, resulting in the unnecessary discarding of valid branch instruction execution information when blocks of instructions are invalidated in the instruction cache.
Innovation Solution
A processor branch prediction circuit that employs back-invalidation of prediction cache entries based on decoded branch instructions, updating the prediction cache entries when there is a mismatch between execution and decode information to maintain accurate branch prediction and reduce idle cycles.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If branch prediction uses prediction cache entries to predict target instructions, then instruction fetch accuracy is improved and idle processor cycles are reduced, but when blocks of instructions are invalidated in the instruction cache, valid branch instruction execution information is unnecessarily discarded
Solution Approach 1:
The patent divides the invalidation process into two separate mechanisms: one for instruction cache blocks and another for prediction cache entries. By segmenting the invalidation logic, the system can selectively invalidate only those prediction cache entries that correspond to actually changed or removed instruction blocks, rather than invalidating all entries associated with a block. This segmentation allows valid branch instruction execution information to be preserved while still maintaining cache coherence.
Solution Approach 2:
The patent applies local quality by making the invalidation behavior specific to individual prediction cache entries rather than applying a global invalidation rule. Each prediction cache entry is evaluated individually to determine if it should be invalidated based on whether its corresponding instruction block has actually changed. This localized approach ensures that only the specific entries affected by instruction cache invalidation are updated, preserving other valid entries.
2Stability of the object's composition
If prediction cache entries are invalidated when instruction cache blocks are invalidated, then cache coherence is maintained, but processor productivity decreases due to loss of valid prediction information
Solution Approach 1:
The patent implements preliminary action by checking whether a prediction cache entry corresponds to an instruction block that has been invalidated before actually invalidating the prediction cache entry. This preliminary verification step prevents unnecessary invalidation of valid prediction information, thereby maintaining processor productivity while still ensuring cache coherence when actually needed.
Solution Approach 2:
The patent uses feedback mechanisms where the instruction decode circuit provides information back to the branch prediction circuit about the validity of prediction cache entries. This feedback loop allows the system to continuously monitor and update prediction cache status based on actual instruction cache state, ensuring coherence is maintained only when necessary and avoiding unnecessary productivity losses.
3Measurement precision
If the prediction cache stores execution information of branch instructions, then branch prediction accuracy is improved, but the device complexity increases due to additional cache management logic
Solution Approach 1:
The patent merges the invalidation management logic with the existing instruction cache validation mechanisms. By combining the prediction cache invalidation logic with the instruction cache block validation that already exists in the processor, the system reduces overall complexity rather than adding separate independent management systems. The merged logic leverages existing infrastructure to manage prediction cache entries.
Solution Approach 2:
The patent makes the prediction cache invalidation mechanism universal by using the same validation and comparison logic that is already employed for instruction cache management. This multi-functional approach allows the system to use existing validation circuits and protocols for both instruction cache and prediction cache management, reducing the need for separate dedicated complexity while maintaining accurate branch prediction.
Data Source
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AI summary
A processor branch prediction circuit employing back-invalidation of prediction cache entries based on decoded branch instructions. Related methods are also disclosed. The execution information of a previously executed branch instruction is obtained from a prediction cache entry and compared to generated decode information in an instruction decode circuit. Execution information of branch instructions stored in the prediction cache entry is updated in response to a mismatch of the execution information and the decode information of the branch instruction. Existing branch prediction circuits invalidate prediction cache entries of a block of instructions when the block of instructions is invalidated in an instruction cache. As a result, valid branch instruction execution information may be unnecessarily discarded. Updating prediction cache entries in response to a mismatch of the execution information and the decode information of the branch instruction maintains the execution information for more accurate branch prediction and fewer idle processor cycles.