Bridge Chip BSPDN Layout for Low-Drop Multichip Power Distribution
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Solution Overview
Problem
Existing multichip semiconductor packaging faces challenges in efficiently distributing power and signals across chips without significant voltage drops, especially when chips require different power levels, and existing technologies struggle to facilitate flexible interconnections.
Innovation Solution
The implementation of a bridge chip with a backside power distribution network (BSPDN) and metal pillars for power and signal distribution, along with an interposer and BEOL/MOL layers, allows for flexible power and signal distribution across multiple semiconductor chips, using copper pillars and hybrid bonds for efficient interconnections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If power is distributed through chips using TSV and TIV to reach far-end chips in a stack, then power can be delivered to multiple chips, but voltage drop becomes unacceptable at the far end of the fan out
Solution Approach 1:
The patent introduces an intermediary bridge chip with a backside power distribution network (BSPDN) that acts as a mediator between the power source and far-end chips. The BSPDN collects power from multiple sources and redistributes it through the bridge chip, preventing excessive voltage drop by providing intermediate power replenishment points in the power distribution path.
Solution Approach 2:
The patent transitions from traditional front-side power distribution to backside power distribution by implementing the BSPDN on the reverse side of the bridge chip. This dimensional change allows power to be delivered from the backside of the chip stack, creating shorter current paths and reducing voltage drop across the chip interconnections.
2Productivity
If chips are stacked on multiple levels with power fanned out to many chips, then more chips can be powered, but the complexity of power distribution increases
Solution Approach 1:
The patent segments the power distribution function by separating the BSPDN on the bridge chip from the individual chip power networks. Each chip maintains its own simplified power distribution, while the bridge chip's BSPDN handles the complex multi-level power collection and redistribution, dividing the overall complexity into manageable segments.
Solution Approach 2:
The bridge chip with BSPDN serves multiple functions simultaneously: it acts as a structural support for stacking, provides power distribution to multiple chips, enables signal interconnection, and facilitates thermal management. This multi-functionality reduces the need for separate dedicated power distribution structures, simplifying the overall system.
3Adaptability or versatility
If flexible power distribution is implemented to accommodate varying power requirements of different chips, then power can be optimized for each chip, but the interconnection structure becomes more complex
Solution Approach 1:
The BSPDN implements local quality by providing different power distribution characteristics to different regions of the bridge chip. Power can be selectively routed to specific chips based on their individual requirements, with the ability to provide higher power to chips needing more energy and lower power to chips with minimal requirements, through locally optimized connection paths.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enables efficient power distribution to chips with varying power requirements and flexible signal transmission, reducing voltage drops and enhancing the functionality of multichip semiconductor structures.
Implementation Method 1
A first plurality of metal pillars connect from certain of the plurality of metal pads on the upper surface of the interposer to certain of the plurality of metal pads on the lower surface of the first and second semiconductor chips. A second plurality of metal pillars connect from certain of the plurality of metal pads on the upper surface of the interposer to certain of the metal pads on the lower surface of the bridge chip.
Implementation Method 2
copper pillars and hybrid bonds for efficient interconnections
Data Source
AI summary
A semiconductor structure includes a first semiconductor chip having a surface with a plurality of conductive features thereon; a second semiconductor chip having a surface with a plurality of conductive features thereon; and a bridge chip coupling the first and second semiconductor chips through the pluralities of conductive features. The bridge chip includes a first surface facing the surfaces of the first and second chips with the conductive features thereon. The bridge chip has a second surface, a BEOL coupled to conductive features on the first surface that are in turn coupled to the pluralities of conductive features, an active device layer having a plurality of devices below the BEOL, a MOL layer in between the active device layer and the BEOL, and a backside power distribution network (BSPDN) below the active layer and coupled to devices on the active layer of the bridge chip.