Bridge Circuit Deadlock Avoidance via Posted Write Bypass
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Solution Overview
Problem
Designers face challenges in implementing suitable data communication arrangements between different portions of programmable integrated circuits using different communication protocols, which can lead to deadlock situations due to ordering rules, particularly when non-posted writes are involved.
Innovation Solution
A bridge circuit is configured to communicate data between circuits using different protocols, where non-posted writes are buffered to prevent deadlock, while posted writes bypass the buffer, allowing for reduced buffer size and preventing communication deadlocks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If all data transactions are buffered to prevent deadlock, then communication reliability is improved, but device complexity and manufacturing cost increase
Solution Approach 1:
The patent segments the buffer circuit into multiple separate buffers, each dedicated to handling specific types of data transactions (posted writes, non-posted writes, reads). This segmentation allows each buffer to be optimized independently and prevents the need for a single large complex buffer that would handle all transaction types, thereby reducing overall device complexity while maintaining communication reliability.
Solution Approach 2:
The patent introduces a transaction type detection mechanism that acts as an intermediary between the communication interface and the buffer circuit. This intermediary identifies whether incoming transactions are posted writes, non-posted writes, or reads, and routes them to appropriate buffers or direct paths, reducing the need for comprehensive buffering of all transaction types and thereby reducing device complexity.
2Reliability
If a large buffer is used to handle all write transactions, then deadlock prevention is improved, but manufacturing cost increases
Solution Approach 1:
The patent divides the buffer resource into multiple smaller specialized buffers instead of using one large general-purpose buffer. Specifically, it creates separate buffers for posted writes and non-posted writes, allowing each buffer to be sized appropriately for its specific function, thereby reducing total manufacturing cost while maintaining effective deadlock prevention.
Solution Approach 2:
The patent applies partial buffering only where necessary to prevent deadlock, rather than buffering all write transactions. By identifying that non-posted writes are the primary source of deadlock conditions and buffering specifically those transactions, the patent achieves adequate deadlock prevention with minimal buffer resources, reducing manufacturing cost.
3Productivity
If non-posted writes are buffered but posted writes bypass the buffer, then productivity is improved, but device complexity increases
Solution Approach 1:
The patent segments the communication path into different routes based on transaction type: a buffered path for non-posted writes and a direct bypass path for posted writes. This segmentation allows posted writes to achieve high throughput by skipping the buffer, while non-posted writes are properly buffered to prevent deadlock, thereby improving overall productivity with manageable complexity.
Solution Approach 2:
The patent introduces a transaction routing mechanism that acts as an intermediary to direct different types of write transactions to appropriate paths. This mediator detects whether a write is posted or non-posted and routes it accordingly, enabling the dual-path architecture that improves productivity while keeping the complexity localized to the routing logic rather than the entire communication path.
Data Source
AI summary
A system is disclosed that includes a first communication circuit that communicates data over a first data port using a first communication protocol. The system also includes a second communication circuit that communicates data over a second data port using a second communication protocol. The second communication protocol processes read and write requests in an order that the read and write requests are received. A bridge circuit is configured to communicate data between the first data port of the first communication circuit and the second data port of the second communication circuit. The bridge circuit is configured to communicate non-posted writes to the second communication circuit via a buffer circuit and communicate posted writes to the second communication circuit via a communication path that bypasses the buffer circuit.