Energy Efficient Computing TRIZ Cases

A neuron circuit uses a threshold-adjustable MOS transistor to implement the ReLU activation function within synaptic arrays.

A USB Type-C interface circuit integrates a multiplexer and control logic to couple configuration channel pins directly to signal terminals.

An image forming apparatus selects industry or place to set default options.

A dedicated sensor polling unit offloads microprocessor tasks by accumulating register data via a global timer, reducing computational burden.

A USB transmitter transitions between idle, standby, and active states based on packet timing to optimize power usage.

SAS expander negotiates PHY power states by routing traffic, reducing consumption without increasing I/O latency.

A data compression method extracts valid bit positions from standard BIER bit strings to form compacted information for network forwarding.

Processor dynamically switches charge IC switching frequency based on battery charging status to reduce idle power consumption.

Pre-built multi-column indexes leverage statistical cost estimation to eliminate slow disk scanning bottlenecks during massive data analysis.

Analog pooling circuitry executes in-place operations within memory blocks to generate output arrays without external data movement.

A direction arbiter sorts read and write commands by destination page to manage data bus transitions in memory systems.

Printer adapts to network security constraints by switching from persistent push connections to periodic pull requests for event notifications.

Compile-time metadata guides asynchronous runtime data block allocation, reducing startup overhead and memory load.

Dynamic pin configuration replaces multiple physical ports, reducing device real estate while maintaining compatibility with evolving interface standards.