Tiled Multicore Processor with Programmable Classification and Shared Token Buckets
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Solution Overview
Problem
Current computing systems face challenges in managing bandwidth efficiently, maintaining cache coherence, and avoiding stalls due to process variations and the limitations of shared memory multiprocessor architectures, particularly in high-performance environments with increasing virtual machines and complex network topologies.
Innovation Solution
Implementing a tiled multicore processor with a programmable classification processor, shared token bucket counter for packet scheduling, and programmable duty cycle adjustment circuits, along with new instructions for load management and cache coherence mechanisms, to enhance performance and scalability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If shared FIFOs with MUTEX locks are used for inter-processor communication, then mutual exclusion and data integrity are ensured, but system performance degrades due to spinning and waiting
Solution Approach 1:
The patent extracts the locking mechanism from the communication path by using lock-free data structures and relaxed memory ordering models. Instead of requiring MUTEX locks for every access, the system uses atomic operations and hardware-supported memory barriers to ensure data integrity without blocking other processors, thereby eliminating spinning and improving throughput
Solution Approach 2:
The patent changes the memory ordering parameters from strict sequential consistency to relaxed ordering models. By adjusting memory barrier placement and using weaker memory ordering guarantees where appropriate, the system reduces the frequency and duration of lock acquisitions while maintaining data integrity, thus improving overall system performance
2Ease of manufacture
If process variations in modern integrated circuit technologies are present, then manufacturing complexity is reduced, but timing precision and maximum clock frequency are limited
Solution Approach 1:
The patent implements dynamic timing adjustment mechanisms that adapt to process variations in real-time. By using programmable delay elements and adjustable clock timing circuits, the system can dynamically compensate for manufacturing variations in different circuit paths, maintaining reliable operation at higher clock frequencies despite process variability
Solution Approach 2:
The patent performs preliminary timing characterization and calibration during manufacturing or initial operation. By pre-adjusting timing parameters and storing compensation values in configuration memory, the system proactively compensates for process variations before they affect high-speed operation, enabling higher clock frequencies without sacrificing reliability
3Adaptability or versatility
If load instructions with long memory access times are used, then data flexibility is improved, but processor stalls increase
Solution Approach 1:
The patent implements preliminary data loading and caching mechanisms. By pre-loading data into local caches or buffer memory before it is needed by the processor, and using predictive prefetching based on access patterns, the system reduces the frequency and duration of stall-inducing memory accesses while maintaining flexible data access capabilities
Solution Approach 2:
The patent enables continuous processor operation by implementing overlapping memory operations with computation. Using double-buffering, stream processing, and persistent memory interfaces, the system maintains data flow continuity so that the processor can continue executing useful instructions while memory operations complete in the background, eliminating idle stall cycles
Data Source
AI summary
A computing system comprises one or more core processors coupled to a communication network among the cores via a switch in each core and switching circuitry to forward data among cores and switches. Features include a programmable classification processor for directing packets, techniques for managing virtual functions on an IO accelerator card, packet scheduling techniques, multi-processor communication using shared FIFOs, programmable duty cycle adjustment and delay adjustment circuits, a new class of instructions that use a ready bit, and cache coherence and memory ordering techniques.